ST72344K2 datasheet(203/247 Pages) STMICROELECTRONICS

203 / 247 page

ST72344xx, ST2345xx

Electrical characteristics

Doc ID 12321 Rev 6

203/247

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by

option byte).

Table 89.

AVD thresholds

Symbol

Parameter

Conditions (1)

TA = -40 to +85°C unless otherwise specified.

Min (2)

Not tested in production, guaranteed by characterization.

Typ

Max (2)

Unit

VIT+(AVD)

1=>0 AVDF flag toggle threshold

(VDD rise)

High threshold

Med. threshold

Low threshold

4.15

3.64

3.00

4.50

3.96

3.28

4.91

4.30

3.54

VIT-(AVD)

0=>1 AVDF flag toggle threshold

(VDD fall)

High threshold

Med. threshold

Low threshold

3.96

3.44

2.85

4.28

3.76

3.11

4.66

4.06

3.35

Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD)

200

ΔV

IT-

Voltage drop between ADV flag

set and LVD reset activated

VIT-(AVD)-VIT-(LVD)

450

Table 90.

PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLIN

PLL Input frequency (1)

Guaranteed by design.

VDD = 2.7 to 3.65 V

PLL option x4 selected

0.95

1.05

MHz

VDD = 3.3 to 5.5 V

PLL option x8 selected

0.90

1.10

VDD(PLL)

PLL operating range

PLL option x4 selected (2)

To obtain a x4 multiplication ratio in the range 3.3 to 5.5V, the DIV2EN option bit must enabled.

2.7

3.65

PLL option x8 selected

3.3

5.5

tw(JIT)

PLL jitter period

fRC = 1 MHz

kHz

JITPLL

PLL jitter (

Δf

CPU/fCPU)

VDD = 3.0 V

3.0

VDD = 5.0 V

1.6

IDD(PLL)

PLL current

consumption

TA=25 °C

600

µA

Table 91.

Internal RC oscillator and PLL

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(RC)

Internal RC oscillator

operating voltage

Refer to operating range

of VDD with TA, Table 87

2.7

5.5

VDD(x4PLL) x4 PLL operating voltage

2.7

5.5

VDD(x8PLL) x8 PLL operating voltage

3.3

5.5

tSTARTUP

PLL Startup time

PLL input

clock (fPLL)

cycles

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