ST72344K2 datasheet(187/247 Pages) STMICROELECTRONICS

187 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

187/247

Changing the conversion channel

The application can change channels during conversion. When software modifies the

CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is

cleared, and the A/D converter starts converting the newly selected channel.

11.8.4

Low-power modes

Note:

The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced

power consumption when no conversion is needed.

11.8.5

Interrupts

None.

11.8.6

Control/status register (ADCCSR)

Reset value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software.

0: fADC = fCPU/4

1: fADC = fCPU/2

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Table 72.

Mode description

Mode

Description

Wait

No effect on A/D Converter

Halt

A/D Converter disabled.

After wakeup from Halt mode, the A/D Converter requires a stabilization time

tSTAB (see Electrical characteristics) before accurate conversions can be

performed.

EOC

SPEED

ADON

CH3

CH2

CH1

CH0

Read/Write (Except bit 7 read only)

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