ST72344K2 datasheet(117/247 Pages) STMICROELECTRONICS

117 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

117/247

Figure 57.

Single master/ single slave application

Slave select management

As an alternative to using the SS pin to control the Slave Select signal, the application can

choose to manage the Slave Select signal by software. This is configured by the SSM bit in

the SPICSR register (see Figure 59).

In software management, the external SS pin is free for other application uses and the

internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

●

In Master mode:

–SS internal must be held high continuously

●

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 58):

If CPHA = 1 (data latched on second clock edge):

–SS internal must be held low during the entire transmission. This implies that in

single slave applications the SS pin either can be tied to VSS, or made free for

standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in

the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):

–SS internal must be held low during byte transmission and pulled high between

each byte to allow the slave to write to the shift register. If SS is not pulled high, a

Write Collision error will occur when the slave writes to the shift register (see Write

collision error (WCOL)).

8-bit SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-bit SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

Not used if SS is managed

by software

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