TMS320VC5416 datasheet(81/98 Pages) TI1

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5.5.10.3

McBSP as SPI Master or Slave Timing

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

tsu(BDRV-BCLXL)

td(BCKXH-BDXV)

th(BCKXL-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXL-BDXHZ)

th(BCKXL-BFXL)

td(BFXL-BDXV)

td(BFXL-BCKXH)

LSB

MSB

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24,

Figure 5-25, Figure 5-26, and Figure 5-27).

Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)

5416-120

5416-160

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low

2 – 6P(2)

th(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low

5 + 12P(2)

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = 0.5 * processor clock.

Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1)

5416-120

5416-160

PARAMETER

UNIT

MASTER(2)

SLAVE

MIN

MAX

MIN

MAX

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low(3)

T – 3

T + 4

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high(4)

C – 4

C + 3

td(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid

– 4

6P + 2(5)

10P + 17(5)

Disable time, BDX high impedance following last data bit from

tdis(BCKXL-BDXHZ)

C – 2

C + 3

BCLKX low

Disable time, BDX high impedance following last data bit from

tdis(BFXH-BDXHZ)

2P– 4(5)

6P + 17(5)

BFSX high

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4P+ 2(5)

8P + 17(5)

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

T = BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even

(3)

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input

on BFSX and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP

CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP

(4)

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the

master clock (BCLKX).

(5)

P = 0.5 * processor clock.

Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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