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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5416 датащи(PDF) 21 Page - Texas Instruments |
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TMS320VC5416 датащи(HTML) 21 Page - Texas Instruments |
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21 / 98 page  Hex 010000 01FFFF Program Page 1 XPC=1 On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) On-Chip DARAM4−7 (MP/MC=0) External (MP/MC=1) Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 020000 02FFFF Page 2 XPC=2 Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 030000 03FFFF Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) External 040000 04FFFF Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 7F0000 7FFFFF Page 3 XPC=3 Page 4 XPC=4 Page 127 XPC=7Fh External 7F7FFF 7F8000 047FFF 037FFF 027FFF 017FFF 018000 028000 038000 048000 On-Chip SARAM0−3 (MP/MC=0) External (MP/MC=1) On-Chip SARAM4−7 (MP/MC=0) External (MP/MC=1) ...... 3.5.1 Relocatable Interrupt Vector Table TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 The extended program memory map is shown in Figure 3-3. Address ranges for on-chip DARAM in data memory are: • DARAM4: 018000h-019FFFh • DARAM5: 01A000h-01BFFFh • DARAM6: 01C000h-01DFFFh • DARAM7: 01E000h-01FFFFh Address ranges for on-chip SARAM in program memory are: • SARAM0: 028000h-029FFFh • SARAM1: 02A000h-02BFFFh • SARAM2: 02C000h-02DFFFh • SARAM3: 02E000h-02FFFFh • SARAM4: 038000h-039FFFh • SARAM5: 03A000h-03BFFFh • SARAM6: 03C000h-03DFFFh • SARAM7: 03E000h-03FFFFh Figure 3-3. Extended Program Memory Map The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. Submit Documentation Feedback Functional Overview 21 |
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