TMS320VC5416 datasheet(33/98 Pages) TI1

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TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

This clock generator allows system designers to select the clock source. The sources that drive the clock

generator are:

• A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins

of the device to enable the internal oscillator.

• An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

NOTE

The crystal oscillator function is not supported by all die revisions of the device. See the

TMS320VC5416 Digital Signal Processor Silicon Errata (literature number SPRZ172) to

verify which die revisions support this functionality.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that

provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock

timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved.

Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

• PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.

• DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL

can be completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock

mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock

module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only

upon the state of the CLKMD1 - CLKMD3 pins. For more programming information, see the TMS320C54x

DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin

configured clock options are shown in Table 3-8.

Table 3-8. Clock Mode Settings at Reset

CLKMD1

CLKMD2

CLKMD3

CLKMD RESET VALUE CLOCK MODE(1)

0000h

1/2 (PLL disabled)

9007h

PLL x 10

4007h

PLL x 5

1007h

PLL x 2

F007h

PLL x 1

0000h

1/2 (PLL disabled)

F000h

1/4 (PLL disabled)

—

Reserved (Bypass mode)

(1)

The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the

clock generation mode can be reconfigured by writing to the internal clock mode register in software.

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