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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5416 датащи(PDF) 47 Page - Texas Instruments |
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TMS320VC5416 датащи(HTML) 47 Page - Texas Instruments |
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47 / 98 page  3.16 McBSP Control Registers and Subaddresses TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register. Table 3-17 shows the McBSP control registers and their corresponding subaddresses. Table 3-17. McBSP Control Registers and Subaddresses McBSP0 McBSP1 McBSP2 SUB- DESCRIPTION ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS SPCR10 39h SPCR11 49h SPCR12 35h 00h Serial port control register 1 SPCR20 39h SPCR21 49h SPCR22 35h 01h Serial port control register 2 RCR10 39h RCR11 49h RCR12 35h 02h Receive control register 1 RCR20 39h RCR21 49h RCR22 35h 03h Receive control register 2 XCR10 39h XCR11 49h XCR12 35h 04h Transmit control register 1 XCR20 39h XCR21 49h XCR22 35h 05h Transmit control register 2 SRGR10 39h SRGR11 49h SRGR12 35h 06h Sample rate generator register 1 SRGR20 39h SRGR21 49h SRGR22 35h 07h Sample rate generator register 2 MCR10 39h MCR11 49h MCR12 35h 08h Multichannel control register 1 MCR20 39h MCR21 49h MCR22 35h 09h Multichannel control register 2 RCERA0 39h RCERA1 49h RCERA2 35h 0Ah Receive channel enable register partition A RCERB0 39h RCERB1 49h RCERA2 35h 0Bh Receive channel enable register partition B XCERA0 39h XCERA1 49h XCERA2 35h 0Ch Transmit channel enable register partition A XCERB0 39h XCERB1 49h XCERA2 35h 0Dh Transmit channel enable register partition B PCR0 39h PCR1 49h PCR2 35h 0Eh Pin control register Additional channel enable register for RCERC0 39h RCERC1 49h RCERC2 35h 010h 128-channel selection Additional channel enable register for RCERD0 39h RCERD1 49h RCERD2 35h 011h 128-channel selection Additional channel enable register for XCERC0 39h XCERC1 49h XCERC2 35h 012h 128-channel selection Additional channel enable register for XCERD0 39h XCERD1 49h XCERD2 35h 013h 128-channel selection Additional channel enable register for RCERE0 39h RCERE1 49h RCERE2 35h 014h 128-channel selection Additional channel enable register for RCERF0 39h RCERF1 49h RCERF2 35h 015h 128-channel selection Additional channel enable register for XCERE0 39h XCERE1 49h XCERE2 35h 016h 128-channel selection Additional channel enable register for XCERF0 39h XCERF1 49h XCERF2 35h 017h 128-channel selection Additional channel enable register for RCERG0 39h RCERG1 49h RCERG2 35h 018h 128-channel selection Additional channel enable register for RCERH0 39h RCERH1 49h RCERH2 35h 019h 128-channel selection Additional channel enable register for XCERG0 39h XCERG1 49h XCERG2 35h 01Ah 128-channel selection Additional channel enable register for XCERH0 39h XCERH1 49h XCERH2 35h 01Bh 128-channel selection Submit Documentation Feedback Functional Overview 47 |
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