TMS320VC5416 datasheet(7/98 Pages) TI1

7 / 98 page

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

List of Tables

2-1

Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package)

......................................... 11

2-2

Signal Descriptions

............................................................................................................... 13

3-1

Standard On-Chip ROM Layout

............................................................................................... 19

3-2

Processor Mode Status (PMST) Register Bit Fields

........................................................................ 22

3-3

Software Wait-State Register (SWWSR) Bit Fields

......................................................................... 24

3-4

Software Wait-State Control Register (SWCR) Bit Fields

.................................................................. 24

3-5

Bank-Switching Control Register (BSCR) Fields

.............................................................................. 25

3-6

Bus Holder Control Bits

.......................................................................................................... 26

3-7

Sample Rate Input Clock Selection

........................................................................................... 32

3-8

Clock Mode Settings at Reset

................................................................................................. 33

3-9

DMD Section of the DMMCRn Register

...................................................................................... 38

3-10

DMA Reload Register Selection

............................................................................................... 41

3-11

DMA Interrupts

................................................................................................................... 42

3-12

DMA Synchronization Events

.................................................................................................. 42

3-13

DMA Channel Interrupt Selection

.............................................................................................. 43

3-14

Device ID Register (CSIDR) Bits

................................................................................................ 44

3-15

CPU Memory-Mapped Registers

................................................................................................ 45

3-16

Peripheral Memory-Mapped Registers for Each DSP Subsystem

........................................................ 45

3-17

McBSP Control Registers and Subaddresses

................................................................................. 47

3-18

DMA Subbank Addressed Registers

........................................................................................... 48

3-19

Interrupt Locations and Priorities

................................................................................................ 50

5-1

Input Clock Frequency Characteristics

......................................................................................... 56

5-2

Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options

....................................... 57

5-3

Divide-By-2 and Divide-By-4 Clock Options Timing Requirements

....................................................... 57

5-4

Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics

................................................... 57

5-5

Multiply-By-N Clock Option Timing Requirements

.......................................................................... 59

5-6

Multiply-By-N Clock Option Switching Characteristics

...................................................................... 59

5-7

Memory Read Timing Requirements

.......................................................................................... 60

5-8

Memory Read Switching Characteristics

..................................................................................... 60

5-9

Memory Write Switching Characteristics

..................................................................................... 63

5-10

I/O Read Timing Requirements

................................................................................................ 64

5-11

I/O Read Switching Characteristics

........................................................................................... 64

5-12

I/O Write Switching Characteristics

............................................................................................ 65

5-13

Ready Timing Requirements for Externally Generated Wait States

...................................................... 66

5-14

Ready Switching Characteristics for Externally Generated Wait States

.................................................. 66

5-15

HOLD and HOLDA Timing Requirements

.................................................................................... 71

5-16

HOLD and HOLDA Switching Characteristics

............................................................................... 71

5-17

Reset, BIO, Interrupt, and MP/MC Timing Requirements

.................................................................. 73

5-18

Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics

........................... 75

List of Tables

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