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PC87570 датащи(PDF) 127 Page - National Semiconductor (TI) |
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PC87570 датащи(HTML) 127 Page - National Semiconductor (TI) |
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127 / 168 page ![]() Digital to Analog Converter (DAC) 127 www.national.com 17.0 Digital to Analog Converter (DAC) The DAC receives digital data and delivers analog signals on four output pins. It includes four independent digital to analog converters. Each of them has 8-bit resolution and a full output range from AGND to AVCC. The DAC has a typi- cal output impedance of 3 K Ω, which allows a settling time of about 1 µs on a 50 pF load. 17.1 FEATURES • 8-bit resolution • 4-channel D/A converter • Fast settling time, 1 µs typical, on 50 pF capacitive load • Output swing from AGND to AV CC • Independent enable/disable for each channel • Zero power when disabled, low power when enabled • Outputs drive zero when disabled 17.2 FUNCTIONAL DESCRIPTION The DAC comprises four independent digital to analog con- verters. The converters drive the four output pins DA0-3, as shown in Figure 17-1. After reset (on power-up or when a positive pulse is applied on the HMR pin), all four channels are disabled and the volt- age on the DA0-3 outputs is 0 V. When a DAC channel is enabled, its output is defined by the value written to its DACDAT Register. DACDAT0 through DACDAT3 control DA0 through DA3, respectively. The maximum output voltage is (255/256)*AVCC and is obtained for a value of FFh. The minimum output, AGND, is obtained for a value of 00h. The reference voltage of the converters is the AVCC analog power supply voltage. This allows full swing of the outputs from zero to nearly AVCC. The Control Register is used to enable/disable each of the four channels. The DAC can be disabled by software before entering Idle mode. 17.2.1 DAC Reset The DACCTRL Register is reset to its default value, in the following two ways: Cold Reset. Upon power-up, an internal power-up detect circuit generates a reset cycle. See Section 2.3 on page 26. Warm Reset. When the chip is powered up and a positive pulse is applied on the HMR pin, a reset cycle is generated. See HMR pin functionality in Table 2-2 on page 21. 17.2.2 Reference Voltage The analog output voltages are converted relative to a ref- erence voltage. See details in Figure 17-1 and Table 19-7 on page 135. The internally connected reference voltage of the DAC is the analog power supply. To assure good signal quality on the DAC outputs, a low noise analog power sup- ply should be used. 17.2.3 Output Signal Range The DAC performs a linear conversion of the input digital value written into the DACDATA0-3 Registers to an un- signed analog output signal. The output signal should be taken relative to the analog ground pin (AGND), and can range from a minimum of AGND to almost AVCC. See Table 19-6 on page 134. A 00h written to the DACDAT0-3 Registers results in an out- put signal of zero (ground) for the respective output. An FFh written to the DACDAT0-3 Registers results in an output signal of (255/256)*AVCC for the respective output. Peripheral Figure 17-1. DAC Functional Diagram DAC0 DA0 DA1 DA2 DA3 AVCC VREF AGND C3 0.1 DAC DACDATA0 Bus PC87570 Analog Power C2 22 + µF 3.3 V or 5.0 V AVCC to other modules µF DAC Control Register DAC1 VREF DACDATA1 DAC2 VREF DACDATA2 DAC3 VREF DACDATA3 IDLE AVCC |
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