PC87570 datasheet(124/168 Pages) NSC

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Analog to Digital Converter (ADC) - January 1998

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Bits 2-0 - Analog Input Channel Select (CHANNEL)

These bits control the input multiplexer and select the

channel to be connected to the Sample and Hold block

(see Figure 16-1). When using a scan mode, it specifies

the first channel to be converted. The software should

configure this field before setting START.

Table 16-4. Analog Input Channel Selection

Bit 3- Reserved

This bit is 0 after reset. Always write zero to this bit.

Bit 4 - Continuous Conversion (CONT)

When set, a new conversion starts after completion of

the current conversion cycle (or conversion burst). The

software should configure this field before setting

START.

0: Single conversion, or one burst of four conversions

1: Continuous conversion

Bits 5 - SCAN

This bit defines whether a single channel or a burst of

four channels is scanned. The software should config-

ure this field before setting START.

0: One channel

1: Four channel scan

Bit 6 - Reserved

This bit is 0 after reset. Always write zero to this bit.

Bit 7 - START

This bit can be set by the software to initiate a conver-

sion cycle. The conversion mode is defined by bits 4 and

5 of this register. The software should not set this bit

while BUSY of the ADCST Register is set.

0: When cleared, the current conversion process is

completed and no subsequent conversion begins

until this bit is set again.

— In single conversion modes (one or four chan-

nels, see bits 4 and 5 of this register), START is

automatically cleared by the hardware upon

completion of the conversion(s).

— In continuous conversion modes, the hardware

does not clear this bit.

1: When set by the software, the conversion process

begins.

16.4.4

ADC Control Register 3 (ADCCNT3)

The ADCCNT3 Register is a byte-wide, read/write register.

ADCCNT3 should be written only when the ADC is disabled

(ADCEN of the ADCCNT1 Register is 0). Upon reset, non-

reserved bits of ADCCNT3 are cleared (0).

Bits 2-0 - ADC Clock Divide (CDIV)

CDIV defines the ratio between the system clock fre-

quency and the ADC clock frequency. The CDIV should

be programmed to guarantee that the ADC conversion

clock is up to 1 MHz. See Figure 16-1 and Chapter 7 on

page 76.

Table 16-5. CDIV Ratios

Bits 5-3 - DELAY

This field allows the user to adjust the sampling time ac-

cording to the external circuits connected to the analog

inputs and the ADC clock frequency.

It defines the delay from setting START or the comple-

tion of previous conversion (in continuous or burst

modes), to the beginning of a new conversion.

The sampling time is defined in terms of ADC clock cy-

cles. It should be used to guarantee the settling time of

the internal sampling circuit. See Section 16.5.5 for fur-

ther details.

Table 16-6. Sampling Time

CHANNEL Bits

Selected Channel

000

001

010

011

100

101

110

111

76543210

Reserved

DELAY

CDIV

CDIV Bits

System Clock to Conversion Clock

Frequency Ratio

000

001

010

011

100

101

Other

Reserved

DELAY Bits

Sampling Time

(Conversion Clock Cycles)

000

001

010

011

100

101

110

Reserved

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