PC87570 datasheet(125/168 Pages) NSC

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Analog to Digital Converter (ADC) - January 1998

125

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16.4.5

ADC Data Registers

The ADC stores the conversion results in four byte-wide,

read only registers, ADDATA0 - ADDATA3. If there is more

than one result, the results are stored in ADDATA0,

ADDATA1, ADDATA2 and ADDATA3 (in this order).

Data is valid only after the EOC flag of ADCST is set. Upon

cold reset (power-up), the contents of these registers is un-

defined. Upon warm reset (using HMR pin), the content of

these registers is not modified. The registers should be ini-

tialized to 00h before enabling them.

16.5 USAGE HINTS

16.5.1

Power Supply and Layout Guidelines

The ADC and the other analog modules are supplied

through two dedicated analog power pins: AVCC and

AGND. This assures effective isolation of the analog mod-

ules from noise caused by the digital modules. To obtain the

best performance, bear in mind the following recommenda-

tions (see also details in Figure 16-4):

Ground Connection. The analog ground pin, AGND,

should be connected at only one point to the digital ground

pins. At this point, also connect the decoupling capacitor of

the analog supply AVCC pin, decoupling capacitor of the ref-

erence voltage VREF pin, and the four decoupling capaci-

tors of the digital supply VCC pins. The ground reference of

the input signals to the ADC should be the same common

point. Low impedance ground layers will also improve noise

isolation.

Power Connection. The analog supply pin, AVCC, should

be connected to a low noise power supply with the same

voltage as the digital supply, either 3.3V or 5.0V. Both the

digital and analog power supplies must be supplied simulta-

neously. To assure this, it is recommended to supply the

AVCC pin from the digital VCC of the chip, using an external

LC or RC filter. An example of an LC filter [L1 and (C2+C3)]

is shown in Figure 16-4.

Figure 16-4. ADC Analog Power Supply Connection

Decoupling Capacitors. The following decoupling capaci-

tors should be used:

Digital VCC: Place one capacitor of 0.1 µF on each

VCC pin, as close as possible to the pin, (4 x C4). Also

place one 10-47

µF tantalum capacitor (C

5) on the

common net, as close as possible to the chip.

Analog AVCC: Place a 0.1 µF capacitor and a 10-

µF tantalum capacitor on the AV

CC pin (C3 and C2)

as close as possible to the pin.

VREF: Place a low leakage, non-polarized, 0.47 µF ca-

pacitor (C1) as close as possible to the VREF pin.

Back-Drive Protection. To maintain the high performance

of the analog circuits, the PD0-7/AD0-7 and VREF pins are

not back-drive protected. Therefore, the voltage on these

pins must be within the actual range of AGND and AVCC. If

it is higher, the chip may be damaged.

External circuits should not drive currents into these pins

when the PC87570 is not powered up. This may cause the

internal power-up reset circuit to fail.

16.5.2

Power Consumption

ADC power consumption from AVCC is practically zero if the

ADC is disabled by clearing the ADCEN bit of the

ADCCNT1 Register. The internal reference is automatically

disabled when ADCEN=0. See Section 16.2.7 on page 121.

When the ADC is enabled, the current consumption de-

pends on the operation mode and the frequency at which it

works. Typical current consumption of the ADC while it is

enabled, but not converting, is 1 mA at AVCC=5V. While

converting in continuous mode, the current consumption is

variable, although typically lower than 2 mA. Typical current

consumption of the internal reference, when enabled, is

0.2 mA.

To minimize current consumption, disable the ADC when

not in use. See details in Section 16.2.7.

76543210

MSB

RESULT 0 DATA

LSB

76543210

MSB

RESULT 1 DATA

LSB

76543210

MSB

RESULT 2 DATA

LSB

76543210

MSB

RESULT 3 DATA

LSB

VCC

GND

Digital Ground Layer

Digital

PC87570

Analog

AVCC

C4 0.1

C3 0.1

AGND

Analog Ground Layer

Power

AD0

AD7

AD0

AD7

VIN

µF

3.3 V

5.0 V

VREF

C1 0.47

µF

L1 10-100 µH

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