PC87570 datasheet(129/168 Pages) NSC

129 / 168 page

Digital to Analog Converter (DAC)

129

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Figure 17-2. DAC Analog Power Supply Connection

Back-Drive Protection. To maintain the high performance

of the analog circuits, the DA0-3 pins are not back-drive pro-

tected. Therefore, the voltage on these pins must be within

the actual range of AGND and AVCC. If it is higher, the chip

may be damaged.

External circuits should not drive currents into these pins

when the PC87570 is not powered up. This may cause the

internal power-up reset circuit to fail.

17.4.2

Output Settling Time

The DAC output settling time depends on the external load

characteristics and the required accuracy. Figure 17-3

shows the equivalent circuit used for evaluating DAC be-

havior. Each DAC output has a typical output impedance of

Ω. For example, if the total load is a 50 pF capacitor

only, the output settles to 1/2 LSB within 1

µs. The total load

capacitance is comprised of the analog output capacitance

(CAO) and the external load capacitance (CL).

17.4.3

Output Voltage Accuracy

The external load on the DA3-0 pins may affect the final out-

put voltage of the DAC. Since the output resistance of these

pins is typically 3 K

Ω, use external high impedance analog

drivers if higher accuracy or output currents are required.

See Table 19-6 on page 134.

For the worst case calculation, if the output resistance is

Ω (maximum limit), the external load must not be lower

than 2 M

Ω. In this case, the error caused by the load is low-

er than 1/2 LSB and there is no need for an external analog

driver.

To work with loads of 5 K

Ω (1 mA at 5 V) with an error lower

than 1/2 LSB, the output resistance of the external driver

should be lower than:

Ω / (2

*256) = 9.8 Ω

17.4.4

Filtering Noise on Output Signals

Output signals may present unwanted noise caused by the

digital circuits they pass nearby. Optionally, when using

slow changing signals in a noisy environment, a low pass fil-

ter (LPF) may be added externally. This may also be re-

quired in applications where the DAC outputs control

sensitive circuits like audio amplifiers. This can be imple-

mented as a simple RC circuit. The cutoff frequency of this

LPF should be above the required signal frequency.

17.4.5

Current Consumption

When a channel is enabled, the current consumption de-

pends on the value set in the DACDAT Register. Minimal

current is consumed when the data is 00h. Maximum cur-

rent is consumed when the data is 55h. In this case, and

when all four channels are enabled with no external load on

the DA0-3 pins, at AVCC=5.0V, the current consumption of

the DAC is typically 5.6 mA (1.4 mA/channel).

The current consumption of any of the DAC channels is

practically zero and its output drives 0 V if one or more of

the following conditions are true:

The chip is in Idle mode (see Chapter 8 on page 79).

The channel is disabled by clearing its corresponding

DACEN bit of the DACCTRL Register.

The value written into its DACDATA Register is 00h.

See Section 17.2.5 for details on disabling the DAC.

17.4.6

Entering Idle Mode

When the chip enters Idle mode, the hardware automatical-

ly disables all four DAC channels and resets the outputs to

drive 0 V, without modifying the DACCTRL or DACDAT

Registers.

When the DAC is disabled, its current consumption from

AVCC is lower than 0.1 µA. More details on how to set

PC87570 to Idle mode are described in Section 8.3.1 on

page 79.

VCC

GND

Digital Ground Layer

Digital

PC87570

Analog

AVCC

C4 0.1

C3 0.1

AGND

Analog Ground Layer

Power

10-100

µH

AD0

µF

3.3 V

5.0 V

AD1

AD2

AD3

DACDAT

Figure 17-3. DAC Output Equivalent Circuit

CAO

AVCC *

256

Application

DAC Output

Equivalent Circuit

Load Circuit

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