PC87570 datasheet(130/168 Pages) NSC

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Development System Support

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18.0 Development System Support

In Dev environment, the PC87570 provides the following

support:

• ISE interrupt input signal

• ISE clipping support via a TRI-STATE pin (TRIS)

• Ability to prevent real-time events from interfering with

the operation of the on-board target monitor (TMON) of

the application development board (ADB)

• Internal information that can be used to implement de-

bug features, e.g., hardware breakpoints.

18.1 ISE INTERRUPT

The ISE interrupt is an edge-triggered non-maskable inter-

rupt that is triggered on the falling edge of the ISE signal. It

is reserved for the development tools and should not be

used as part of the application.

The ISE interrupt is enabled in the Development environment

when DBGCFG.ON bit is set. Otherwise, it is ignored.

18.2 TRIS STRAP INPUT PIN

The TRIS strap input pin is used by ISEs to allow clipping

on a PC87570 while mounted in the system.

The TRIS input is a strap pin sampled at power-up reset.

When TRIS is low (0), the PC87570 acts normally. When

TRIS is high (1), all the PC87570 outputs are put to

TRISTATE.

Setting TRIS to the required value is described in Section

2.4 on page 26

18.3 FREEZING EVENTS

The PC87570 prevents real-time events from interfering

with the operation of the ADB’s TMON and changing the

status of the PC87570, by disabling maskable interrupts,

freezing the WATCHDOG counter and disabling destructive

read operations.

18.3.1

Disabling Maskable Interrupts

Clearing the core’s PSR.I bit or PSR.E bits disable the

maskable interrupts. The PSR.I bit is cleared automatically

whenever a trap or interrupt occurs and after reset.

18.3.2

Freezing the WATCHDOG Counter

To freeze the WATCHDOG counter, set DBGCFG.FREEZE

to 1 on entering an ADB TMON routine. Then clear it to 0,

before returning to the application. This prevents the

WATCHDOG generating the reset that occurs if it is not

cleared in time (See Section 15.3 on page 117.) The

WATCHDOG counter keeps its value while it is frozen, and

resumes counting after DBUGCFG.FREEZE is cleared to 0.

If an application fails to refresh the WATCHDOG in time, and

a reset interrupt is generated before or while the FREEZE bit

is set, the PC87570 executes WATCHDOG reset.

18.3.3

Disabling Additional Modules

The MFT16 and ACB modules may be frozen by the

FREEZE bit. This freeze is enabled only when the respec-

tive bit in the DBGFRZEN Register is set, to meet specific

usage of the module by different applications.

18.3.4

Disabling Destructive Reads

When the DBGCFG.FREEZE is set (1), destructive reads

do not change the system’s state (i.e., they only return the

read data but do not clear or set bits or send signals). This

allows the ISE system to present the values of these bits.

NMISTAT is an exception to this rule, and is not affected by

FREEZE. CR16A accesses to RTC registers may also be

destructive, but are not affected by the FREEZE. Note that

host operations continue without any FREEZE bit impact.

18.4 MONITORING ACTIVITY DURING DEVELOPMENT

In Dev environment, information is available for monitoring

on-chip activities and implementing debug features in the

development system.

18.4.1

The Bus Status Signals

The Bus Status BST(0-2) signals indicate if a transaction on

the core bus was issued and if so, the type of transaction.

The BST(0-2) signals reflect activity on the core bus. For word

accesses involving 8-bit Expansion Memory, the core bus cy-

cle triggers two external bus cycles. The first external bus cycle

is flagged as a T1 cycle of the core bus. The second is not

flagged as a T1 cycle of the core bus, i.e., BST(0-2) is 000. See

Table 18-1.

Table 18-1. Core Bus Transaction Encoding

18.4.2

Transaction Effects on the External Bus

The following core bus transactions are reflected on the ex-

ternal bus:

• Accesses to external zones of External Memory, off-

chip Base Memory, and accesses that use the I/O Ex-

pansion protocol are indicated by the active state of the

SEL0, SEL1 and SELIO signals, respectively, and are

described by the address and data buses.

• Accesses to on-chip memories and peripheral modules

are observed using the “Core Bus Monitoring Bus Cy-

cles” (see the BIU, Section 3.4 on page 44). They are in-

dicated by an inactive state for the SEL0, SEL1, and/or

SELIO signals. They are described by addresses A(0-

12), the byte enable BE(0-1) signals, the CBRD signal

and the BST(0-2) signals.

• BE0 is high when a lower memory byte (a byte in an

even address) is accessed. BE1 is high when a higher

memory byte (a byte in an odd address) is accessed.

• CBRD is high when the transaction is a read operation

or low when it is a write.

BST

Core Bus Transaction Type

000

Not a T1 cycle, except for when CR16A waits for

an interrupt following WAIT instruction execution

001

CR16A waits for an interrupt following WAIT

instruction execution

010

T1 of an interrupt acknowledge bus cycle

011

T1 of a data transfer of a non-core

100

T1 of a sequential instruction fetch

101

T1 of a non-sequential instruction fetch

110

T1 of a CR16A data transfer

111

T1 of an exception data transfer

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