PC87570 datasheet(123/168 Pages) NSC

123 / 168 page

Analog to Digital Converter (ADC) - January 1998

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16.4 ADC REGISTERS

The ADC interfaces with the CR16A core, as shown in the

"Block Diagram" on page 1. The interface is implemented by

a set of four status and control registers, and four data reg-

isters. These registers are mapped in the address space of

the CR16A. For details on the address location of these reg-

isters, refer to Appendix A on page 156.

16.4.1

ADC Status Register (ADCST)

This is a is a byte-wide, read/write register that reports the

ADC status. Upon reset, the non-reserved bits are cleared

Bit 0 - End of Conversion (EOC)

This bit reports the ADC conversion status. This bit is

read only and data written to it is ignored. It is written by

the hardware as follows:

0: Conversion is not complete. It is also cleared when

any of the data registers is read.

1: Conversion is complete. Indicates that the data was

placed in the buffer.

Bit 1 - BUSY

This flag indicates that the ADC is busy converting data.

It is a read only bit and any data written to it is ignored.

It is written by the hardware as follows:

0: ADC is not busy and a new conversion can be

started. This bit is cleared whenever:

— ADC is disabled, (ADCEN of the ADCCNT1

— ADC is idle, (i.e., ADC is enabled, ADCEN=1,

and not converting).

1: ADC is busy converting. START should not be set

before completion of the current conversion.

Bit 2 - Overﬂow (OVF)

0: This bit remains set until the software writes 1 to it.

Writing 0 has no effect on this bit.

1: The ADC finished conversion and attempted to

store the result in a data register (ADDATA0-3), but

it was full. A data register is full if it was written by

the ADC and was not read by the CR16A core. In

this case, the ADC overrides the data in the ADDA-

TAn Register, sets OVF and continues operation.

Bits 5-4 - Buffer Pointer (BUFPTR)

BUFPTR holds the number of the last written data reg-

ister (ADDATA0-3). BUFPTR is set to 11 when START

of the ADCCNT2 Register is changed from 0 to 1. It is a

read only field; data written to it is ignored.

16.4.2

ADC Control Register 1 (ADCCNT1)

This is a byte-wide, read/write register that enables the ADC

and the internal reference. In addition, it configures the in-

terface scheme. Changing bits 1 through 7 of ADCCNT1

while the module is active is not allowed. The ADC is active

while START of the ADCCNT2 Register or BUSY of the

ADCST Register are set. Upon reset, the non-reserved bits

of ADCCNT1 are cleared.

Bit 0 - ADC Enable (ADCEN)

0: When the software clears this bit, the ADC is dis-

abled and the current conversion operation is ter-

minated. The status flags EOC, BUSY and OVF in

the ADCST Register and START of the ADCCNT2

to disable the ADC only when it is in Idle mode (not

converting, START and BUSY are both 0). See

Figure 16-3.

1: When the software sets this bit, the ADC is en-

abled. Conversion can be started as described in

Section 16.2.6.

Bit 1 - Internal VREF (INTREF)

This read/write bit selects the source of the reference

voltage. See also Figure 16-1 and Section 16.2.2.

Note: INTREF can be changed independently of AD-

CEN. However, the internal reference block is turned on

only when the ADC is enabled (ADCEN is set to 1).

Since an external capacitor is present on the VREF pin,

there is a delay of approximately 50

µs until the voltage

on the pin stabilizes after INTREF is set. See Section

16.2.5 on page 120.

0: An external reference voltage should be connected

to VREF pin, as a reference voltage for the ADC op-

eration. In this case, the internal reference voltage

source is disabled and does not drain power.

1: Enables the on-chip reference voltage source and

connects it to the DAC input.

Bit 2 - Interrupt Enable (INTE)

This bit controls interrupt generation to the CR16A core.

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