PC97338 datasheet(180/221 Pages) NSC

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IRCFG1 – Infrared Interface Configuration

This register holds the transceiver configuration data

for Sharp-IR and SIR Modes.

When automatic configuration is not enabled, it is

used to directly control the transceiver operational

mode. The least significant four bits are also used to

read the identification data of a Plug-n-Play infrared

adapter.

FIGURE 88. Infrared Configuration Register 1

IRCFG2 – Infrared Interface Configuration

This register holds the transceiver configuration data

for MIR and FIR Modes.

FIGURE 88. Infrared Configuration Register 2

IRIC0 – Transceiver Identification/Control.

The function of this bit depends on whether the

ID0/IRSL0/IRRX2 pin is programmed as an in-

put or as an output.

ID0/IRSL0/IRRX2 Pin Programmed as Input

(IRSL0_DS = 0).

Upon read, this bit returns the logic level of

the pin.

Data written into this bit position is ignored.

ID0/IRSL0/IRRX2 Pin Programmed as Output

(IRSL0_DS = 1).

If AMCFG is set to 1, this bit will drive the

ID0/IRSL0/IRRX2 pin when Sharp-IR Mode

is selected.

If AMCFG is 0, this bit will drive the

ID0/IRSL0/IRRX2 pin regardless of the se-

lected mode.

Upon read, this bit returns the value previously

written.

B2–1 IRIC[2–1] – Transceiver Identification/Con-

trol

The function of these bits depends on whether

the ID/IRSL[2–1] pins are programmed as in-

puts or as outputs.

ID/IRSL[2–1] Pins Programmed as Inputs

(IRSL21_DS = 0).

Upon read, these bits return the logic levels of

the pins.

Data written into these bit positions is ignored.

ID/IRSL[2–1] Pins Programmed as Outputs

(IRSL21_DS = 1).

321

Reset

Required

IRIC(2-0)

SIRC(2-0)

STRV_MS

If AMCFG is set to 1, these bits will drive the

ID/IRSL[2–1] pins when Sharp-IR Mode is se-

lected.

If AMCFG is 0, these bits will drive the

ID/IRSL[2–1] pins regardless of the selected

mode.

Upon read, these bits return the values previ-

ously written.

B6–4 SIRC [2–0] – SIR Mode Transceiver Config-

uration.

These bits will drive the ID/IRSL[2–0] pins

when AMCFG is 1 and SIR Mode is selected.

They are unused when AMCFG is 0 or when

the ID/IRSL[2–0] pins are programmed as in-

puts.

Upon read, these bits return the values previ-

ously written.

STRV_MS – Special Transceiver Mode Se-

lect.

This bit is used to select the operational mode

in high speed optical transceiver modules.

When this bit is set to 1, the IRTX output is

forced high and a timer is started.

The timer times out after approximately 64

µs,

at which time the bit is reset and IRTX returns

low. The timer is restarted every time a 1 is

written into this bit position. Therefore, the time

in which IRTX is forced high can be extended

beyond 64

µs.

This should be avoided, however, to prevent

damage to the transmitter LED.

Writing 0 into this bit position has no effect.

B2–0 MIRC [2–0] – MIR Mode Transceiver Config-

uration.

These bits will drive the ID/IRSL[2–0] pins

when AMCFG is 1 and MIR Mode is selected.

321

Reset

Required

MIRC(2-0)

FIRC(2-0)

Reserved

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