PC97338 datasheet(148/221 Pages) NSC

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The FIR transmitter front-end section adds the Pre-

amble as well as Start and Stop flags to each frame

and encodes the transmit data into a 4PPM (Four

Pulse Position Modulation) data stream. The FIR re-

ceiver front-end section strips the Preamble and flags

from the inbound data stream and decodes the 4PPM

data while also checking for coding violations.

Both MIR and FIR front-ends also automatically ap-

pend CRC sequences to transmitted frames and

check for CRC errors on received frames.

5.6.1

High Speed Infrared Transmit

Operation

When the transmitter is empty, if either the CPU or the

DMA controller writes data into the TX_FIFO, trans-

mission of a frame will begin. Frame transmission can

be normally completed by using one of the following

methods:

1. S_EOT bit (Set End of Transmission). This

method is used when data transfers are performed

in PIO mode. When the CPU sets the S_EOT bit

before writing the last byte into the TX_FIFO, the

byte will be tagged with an EOF indication. When

this byte reaches the TX_FIFO bottom, and is read

by the transmitter front-end, a CRC is appended to

the transmitted DATA and the frame is normally

terminated.

2. DMA TC Signal (DMA Terminal Count). This

method is used when data transfers are performed

in DMA mode. It works similarly to the previous

method except that the tagging of the last byte of

a frame occurs when the DMA controller asserts

the TC signal during the write of the last byte to the

TX_FIFO.

3. Frame Length Counter. This method can be

used when data transfers are performed in either

PIO or DMA mode. The value of the FEND_MD bit

in the IRCR2 register determines whether the

Frame Length Counter is effective in the PIO or

DMA mode. The counter is loaded from the Frame

Length Register (TFRL) at the beginning of each

frame, and it is decremented as each byte is trans-

mitted. An EOF is generated when the counter

reaches zero. When used in DMA mode with an

8237 type DMA controller, this method allows a

large data block to be automatically split into

equal-size back-to-back frames, plus a shorter

frame that is terminated by the DMA TC signal, if

the block size is not an exact multiple of the frame

size.

An option is also provided to stop transmission at

the end of each frame. This happens when the

transmitter Frame-End stop mode is enabled

(TX_MS bit in the IRCR2 register set to 1). By us-

ing this option, the software can send frames of

different sizes without re-initializing the DMA con-

troller for each frame. After transmission of each

frame, the transmitter stops and generates an in-

terrupt. The software loads the length of the next

frame into the TFRL register and restarts the

transmitter by clearing the TXHFE bit in the ASCR

Note: PIO or DMA mode is only controlled by the set-

ting of the DMA_EN bit in the extended-mode MCR

cles the same except that DMA cycles always access

the TX or RX_FIFO, regardless of the selected bank.

When DMA_EN is set to 1, the CPU can still access

the TX_FIFO and RX_FIFO. The CPU accesses will,

however, be treated as DMA accesses as far as the

function of the FEND_MD bit is concerned.

While a frame is being transmitted, data must be writ-

ten to the TX_FIFO at a rate dictated by the transmis-

sion speed. If the CPU or DMA controller fails to meet

this requirement, a transmitter underrun will occur, an

inverted CRC is appended to the frame being trans-

mitted, and the frame is terminated with a Stop flag.

Data transmission will then stop. Transmission of the

inverted CRC will guarantee that the remote receiving

module will receive the frame with a CRC error and

will discard it.

Following an underrun condition, data transmission

always stops at the next frame boundary. The frame

bytes from the point where the underrun occurred to

the end of the frame will not be sent out to the external

infrared interface. Nonetheless, they will be removed

from the TX_FIFO by the transmitter and discarded.

The underrun indication will be reported only when

the transmitter detects the end of frame via one of the

methods described above. The software can do vari-

ous things to recover from an underrun condition. For

example, it can simply clear the underrun condition by

writing a 1 into bit 6 of ASCR and re-transmit the un-

derrun frame later, or it can re-transmit it immediately,

before transmitting other frames.

If it chooses to re-transmit the frame immediately, it

needs to perform the following steps:

1. Disable DMA controller, if DMA mode was select-

ed.

2. Read the TXFLV register to determine the number

of bytes in the TX_FIFO. (This is needed to deter-

mine the exact point where the underrun occurred,

and whether or not the first byte of a new frame is

in the TX_FIFO).

3. Reset TX_FIFO.

4. Backup DMA controller registers.

5. Clear Transmitter underrun bit.

6. Re-enable DMA controller.

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