PC97338 datasheet(127/221 Pages) NSC

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Bit 1 - Automatic Line Feed Control

This bit directly controls the automatic line feed

signal to the printer via the AFD pin. Setting this bit

high causes the printer to automatically feed after

each line is printed.

This bit is the inverse of the AFD pin.

0 - No automatic line feed. (Default)

1 - Automatic line feed

Bit 2 - Printer Initialization Control (INIT)

This bit directly controls the signal to initialize the

printer via the INIT pin. Setting this bit to low initial-

izes the printer.

The value of the INIT signal reflects the value of this bit.

In the PC87338 this bit is 0 after reset (activate

INIT sig-

nal to initialized the printer).

In the PC97338 this bit is 1 after reset, so the printer can

stay in ECP mode if it was programmed to this mode,

and not initialized to SPP mode.

0 - Initialize Printer (Default in PC87338).

1 - No action (Default in PC97338).

Bit 3 - Select Input Signal Control

This bit directly controls the select in signal to the

printer via the SLIN pin. Setting this bit high selects

the printer.

It is the inverse of the SLIN pin.

This bit must be set to 1 before enabling the EPP

or ECP modes via bits 0 or 2 of the PCR register.

0 - Printer not selected. (Default)

1 - Printer selected and online.

Bit 4 - Interrupt Enable

Bit 4 controls the interrupt generated by the ACK

signal. Its function changes slightly depending on

the parallel port mode selected.

In ECP mode, this bit should be set to 0.

In the following description, IRQx indicates an in-

terrupt line allocated for the parallel port.

0 - In Compatible SPP, Extended SPP and EPP

modes, IRQx is floated. (Default)

1 - In Compatible SPP mode, IRQx follows ACK

transitions.

In Extended SPP mode, IRQx is set active on

the trailing edge of ACK.

In EPP mode, IRQx follows ACK transitions, or

is set when an EPP time-out occurs.

Bit 5 - Direction Control

This bit determines the direction of the parallel port

in Extended SPP mode (when bit 7 of PTR is 1). In

the (default) Compatible SPP mode, this pin has

no effect, since the port functions for output only.

This is a read/write bit in EPP modes. In SPP

modes it is a write only bit. A read from it returns 1.

In Compatible SPP mode and in EPP modes it

does not control the direction. See Table 64.

0 - Data output to PD7-0 in Extended SPP mode

during write cycles (Default)

1- Data input from PD7-0 in Extended SPP mode

during read cycles.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

4.3

ENHANCED PARALLEL PORT

(EPP) MODES

EPP modes allow greater throughput than Compati-

ble SPP and Extended SPP modes by supporting

faster transfer times (8, 16 or 32 bit data transfers in

a single read/write operation) and a mechanism that

allows the system to address peripheral device regis-

ters directly. Faster transfers are achieved by auto-

matically generating the address and data strobes.

The connector pin assignments for these modes are

listed in “Parallel Port Pin Out” on page 145.

EPP modes support revision 1.7 and revision 1.9 of

the IEEE 1284 standard, as shown in Table 65. When

bit 5 of FCR is 1 (configured for zero wait states), the

EPP revision is always 1.7, i.e., it is not affected by bit

1 of PCR.

TABLE 65. EPP Revision Selection

In Legacy mode, EPP modes are supported for a par-

allel port whose base address is 278h or 378h, but not

for a parallel port whose base address is 3BCh.

(There are no EPP registers at 3BFh.)

SPP-type data transactions may be conducted in ei-

ther EPP mode. The appropriate registers are avail-

able for this type of transaction. (See Table 66.) As in

the SPP modes, software must generate the control

signals required to send or receive data.

The output of the control signals in PC87338 are in

level 2 (pushpull) when in EPP1.9 mode

The output of the control signals in PC97338 are in

level 2 (pushpull) always when in EPP mode.

EPP Mode

Bit 5 of the FCR

Configuration

Bit 1 of

PCR

Bit 0 of

PCR

EPP Revision

1.7

EPP Revision

1.9 (IEEE 1284)

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