Register description

L2G2IS

20/26

DocID027248 Rev 2

7.6

CTRL_REG1 (0Bh)

Table 16. STATUS_REG description

YXOR

X-, Y-axis data overrun.

(0: no overrun has occurred; 1: new data has overwritten the previous data before it was

read)

XOR

X-axis data overrun.

(0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data)

YOR

Y-axis data overrun.

(0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data)

YXDA

X-, Y-axis new data available.

(0: a new set of data is not yet available; 1: a new set of data is available)

XDA

X-axis new data available.

(0: new data for the X-axis is not yet available; 1: new data for the X-axis is available)

YDA

Y-axis new data available.

(0: new data for the Y-axis is not yet available;1: new data for the Y-axis is available)

Table 17. CTRL_REG1 register

BOOT

P_DRDY

BLE

SIM

ODU

1. This bit must be set to ‘0’ for proper operation of the device.

PW1

PW0

Table 18. CTRL_REG1 description

BOOT

Reboot memory content. Default value: 0

1. Boot request is executed as soon as internal oscillator is turned-on. It is possible to set this bit while in

power-down mode, in this case it will be served at the next normal mode or sleep mode.

P_DRDY

DRDY signal pulsed. Default value: 0

(0: DRDY is latched; 1: DRDY is pulsed)

BLE

Big/little endian data selection. Default value: 0

(0: Data LSB @ lower address; 1: Data MSB @ lower address)

SIM

SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

ODU

Output data update. Default value: 0

(0: output registers not updated until MSB and LSB have been read;

1: output registers updated continuously)

PW[1:0]

Operating mode selection. Default value: 00

Refer to Table 19: Operating mode selection.