ADP3500

REV.PrP 2/6/02

- 27 -

2.11 REGISTERS

ADDR

Description

D7

D6

D5

D4

D3

D2

D1

D0

Comment

00h

Sec. Counter

S5

S4

S3

S2

S1

S0

Note 1,5

01h

Min. Counter

M5

M4

M3

M2

M1

M0

Note 1,5

02h

Hour Counter

H4

H3

H2

H1

H0

Note 1,5

03h

Week Counter

W2

W1

W0

Note 1,5

04h

Day Counter

D4

D3

D2

D1

D0

Note 1,5

05h

Month Counter

MO3

MO2

MO1

MO0

Note 1,5

06h

Year Counter

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Note 1,5

07h

Alarm_A Min Register

AM5

AM4

AM3

AM2

AM1

AM0

Note 5

08h

Alarm_A Hour Register

AH4

AH3

AH2

AH1

AH0

Note 5

09h

Alarm_A Week Register

AW6

AW5

AW4

AW3

AW2

AW1

AW0

Note 5

0Ah

Alarm_B Min Register

BM5

BM4

BM3

BM2

BM1

BM0

Note 5

0Bh

Alarm_B Hour Register

BH4

BH3

BH2

BH1

BH0

Note 5

0Ch

Alarm_B Week Register (Option)

BW6

BW5

BW4

BW3

BW2

BW1

BW0

Note 5

0Dh

Alarm Control

ALA_EN

Aout

ALB_EN

Bout

Note 5

0Eh

Periodic Interrupt Control

CTFG

CT2

CT1

CT0

Note 5

0Fh

Stay-Alive Timer Control

CLR

SA4

SA3

SA2

SA1

SA0

Note 5

10h

Charger Control

CHI

CHEN

Note 4

11h

Charger MVBAT Control

REF0

MVEN

Note 4

12h

Charger MVBAT

CHV1

CHV0

MV4

MV3

MV2

MV1

MV0

Note 4

13h

LDO Control 1

LDO11

LDO5

LDO4

Note 4

14h

Not available

Note 7

15h

LDO Control 2

LDO10

LDO9

LDO8

LDO7

Note 4

16h

LDO Control 3

ALLOF

F

Note 4

17h

LDO2 Gain

G23

G22

G21

G20

Note 4

18h

Keypad Column/B-light Register

BL

KO3

KO2

KO1

KO0

Note 6

19h

Keypad Row

KI5

KI4

KI3

KI2

KI1

KI0

Note 6

1Ah

GPIO Control Register

GPC3

GPC2

GPC1

GPC0

Note 6

1Bh

GPIO MASK

GPMSK3

GPMSK2

GPMSK1

GPMSK

0

Note 6

1Ch

GPIO Register

GPI3

GPO3

GPI2

GPO2

GPI1

GPO1

GPI0

GPO0

Note 6

1Dh

GPIO INT

GPINT3

GPRST3

GPINT2

GPRST2

GPINT1

GPRST1

GPINT0

GPRST0

Note 2,6

1Eh

INT Register

IN

T7

IR

ST

7

INT6

IRST6

INT5

INT4

INT3

IRST3

INT2

IRST2

INT1

IRST1

INT0

IRST0

Note 2,6

1Fh

INT MASK

MS

K7

MSK6

MSK5

MSK4

MSK3

MSK2

MSK1

MSK0

Note 6

20h

DATA IN

DI6

DI5

DI4

DI3

DI2

DI1

DI0

Note 6

21h

Power OFF

PWROF

F

Note 6

3Fh

TEST register (option)

LDOENB

USENB

TEST

Note 3,5

Notes:

1. For the RTC counter data protection, the access should be waited for certain time (62

µS) period after CS signal assertion.

(Refer to RTC counter section for the wait time).

2. The INT reset operation will be valid at 62

µS or later after its setting.

3. This is a set register for internal test, and should not be accessed at normal operation.

4. Analog block control registers. They control LDO etc. They are powered by VBAT.

5. Registers regarding RTC counter. They are powered by RTCV.

6. Registers for INT, GPIO, KEYPAD I/F etc. They are powered by VBAT.

7. Not available.

PRELIMINARY TECHNICAL DATA