ADP3500

REV.PrP 2/6/02

- 25 -

addr06h_write

USEC

counter

addr00h_write

7 scale

31 scale

12 scale

100 scale

00h

01h

02h

03h

04h

05h

06h

month_count

year_count

day_count

hour_count

week_count

min_count

sec_count

Enabled signals created

by decoding of

RTC_SP_ADDR[5:0]

Initial data

12 scale

60 scale

60 scale

Leap year

&

days in month

control

inc_enb

inc_clk

To following

counters

Year

Month

Date

Week

Hour

Minute

Second

Figure 16. RTC counter block diagram

Definition of Leap year

The definition of a leap year is, “a year which can be divided by 4 and can not be divided by 100” and “a year which can be

divided by 400.” For this device, the following definition is used instead.

“A year which can be divided by 4”

Note

-

Year counter = “00” means year 2000, and is a leap year because it can be divided by 400.

-

Actual covered year period is from 1901 to 2099.

Number of days of month control

Months 1, 3, 5, 7, 8, 10, 12 have 31days.

Months 4, 6, 9, 11 have 30days.

Month 2 has 28days, but has 29 in leap year.

2.9.5 Alarm Function

Comparing the RTC counter value with the seting value in alarm_setting register (07h-09h), alarm condition is detected.

Setting of week uses 7bits for each day in a week, and works with multiple days setting. There is a delay of 62

µSfrom Alarm

detection to setting up to AOUT/BOUT registers.

ALA_EN flag in ALARM CONTROL register (0Dh) sets Enable/Disable of alarm detection. INT register (1Eh) indicates the

interrupt signals, alarm_int of ALA or/and ALB. INT MASK register (1Fh) do mask of alarm interrupt signal. Alarm

detection state is indicated as AOUT of ALARM CONTROL register (0Dh), and the alarm can be released by writing “1” at

the bit. Alarm B is also controlled as same as Alarm A is.

Note:

User just need to write “1” to release the alarm, and not need to write “0” after “1”. User doesn’t need to wait 62

µS

from CS assertion.

2.9.6 Periodic Interrupt function

This is a function, which generates interrupt periodically. The timing of cycle can be selected from 2Hz (0.5sec clock pulse),

1Hz (1sec clock pulse), 1/60Hz (minutes), 1/3600Hz (hour), and month (first day of each month).

The cycle is set using CT2-CT0 value in CTFG CONTROL register (0Eh). The state when interrupt is generated is indicated at

INTRA bit of CTFG CONTROL register (0Eh). INT MASK register (1Fh) only does mask of periodic interrupt signal. There

are two kinds of pattern of CTFG Interrupt signal output.

•

Hold the value when the interrupt is occurred (level).

•

After the interrupt event is happened, assert interrupt signal in certain time period then release it (pulse).

PRELIMINARY TECHNICAL DATA