ADP3500

REV.PrP 2/6/02

- 26 -

In level case, interrupt is occurred at each 0 min (1/60Hz), 0 o’clock (1/3600Hz) or at first day of month. Because they are

happened in long cycle, the value is held at register. After the CPU checks the state, it is released by writing “1” at CTFG bit

of CTFG CONTROL register. In case of 2Hz and 1Hz, the interrupt is not held because the event happens in short cycle.

These event signal output pulse signal of 2Hz or 1Hz in RTC counter directly. Interrupt release operation doesn’t affect on the

interrupt signal in the case.

2.10 STAY-ALIVE TIMER

This is a counter, which increments each 250mS after RTC_RESETIN_N is asserted. It holds its value when the counter

counts full up. Signal clk4 is a 4Hz (250mS) clock which generated in USEC counter. The counter can be reset by writing “1”

at CLR of Stay-Alive TIMER CONTROL register (0Fh). The RTC_RESETIN_N signal is transferred from a logic input

circuit, that is supplied by VBAT, of RESETIN_N.

Note

:

User just need to write “1” to release the interrupt, and not need to write “0” after “1”.

5bit counter

test_reset

clk4

CLRB

D

SA[4:0]

RTC_RESETIN_N

Register

Stay-Alive Timer

Stay-alive Timer Control register (0Fh): CLR

Stay-alive Timer Control register (0Fh): SAx

Figure 17. Stay-Alive Timer block diagram

clk4

sa_count[4:0]

sa_clear

3

2

1

0

431

530

0

rtc_voltage_detect

Figure 18. Stay-Alive Timer operation timing

PRELIMINARY TECHNICAL DATA