Preliminary Technical Data

AD7265

MODES OF OPERATION

The mode of operation of the AD7265 is selected by controlling

the (logic) state of the CS signal during a conversion. There are

three possible modes of operation: normal mode, partial power-

down mode, and full power-down mode. The point at which CS

is pulled high after the conversion has been initiated determines

which power-down mode, if any, the device enters. Similarly, if

already in a power-down mode, CS can control whether the

device returns to normal operation or remains in power-down.

These modes of operation are designed to provide flexible

power management options. These options can be chosen to

optimize the power dissipation/throughput rate ratio for

differing application requirements.

accessed on the same DOUT line, as shown in Figure TBD (see

the Serial Interface section). The identification bit provided

prior to each conversion result identifies which on-board ADC

the following result is from. Once 32 SCLK cycles have elapsed,

edge. If CS is brought high prior to this, the DOUT line returns

to three-state at that point. Thus, CS may idle low after 32 SCLK

cycles until it is brought high again sometime prior to the next

conversion (effectively idling CS low), if so desired, since the

bus still returns to three-state upon completion of the dual

result read.

returned to three-state, another conversion can be initiated after

NORMAL MODE

This mode is intended for fastest throughput rate performance

since the user does not have to worry about any power-up times

with the AD7265 remaining fully powered all the time. Figure 8

shows the general diagram of the operation of the AD7265 in

this mode.

PARTIAL POWER-DOWN MODE

110

14

LEADING ZERO, I.D. BIT + CONVERSION RESULT

CS

SCLK

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of several conversions. When the AD7265 is in partial

power-down, all analog circuitry is powered down except for

the on-chip reference and reference buffer.

To enter partial power-down, the conversion process must be

interrupted by bringing CS high anywhere after the second

shown in Figure 9. Once CS has been brought high in this

window of SCLKs, the part enters partial power-down, the

conversion that was initiated by the falling edge of CS is

CS is brought high before the second SCLK falling edge, the

part remains in normal mode and does not power down. This

avoids accidental power-down due to glitches on the CS line.

Figure 8. Normal Mode Operation

The conversion is initiated on the falling edge of CS, as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times, CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

required to complete the conversion and access the conversion

result. The DOUT line does not return to three-state after 14

SCLK cycles have elapsed, but instead does so when CS is

brought high again. If CS is left low for another 2 SCLK cycles

(e.g. if only a 16 SCLK burst is available), two trailing zeros are

clocked out after the data. If CS is left low for a further 16 SCLK

cycles again, the result from the other ADC on board is also

1

2

10

14

CS

SCLK

TRI-STATE

Figure 9. Entering Partial Power-Down Mode

Rev. PrA | Page 13 of 16