Preliminary Technical Data

AD7265

Pin No.

Mnemonic

Description

21

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog

input channels will have. On the falling edge of CS , the polarity of this pin is checked to determine the analog

input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin

25–23

A0–A2

Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted

simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of

channels selected may be two single ended channels or two differential pairs. The logic states of these pins are

checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. See Table 6 for

multiplexer address decoding.

22

SGL/DIFF

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic

low selects differential operation while a logic high selects single ended operation.

2

REF SELECT

Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as

capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265

Rev. PrA | Page 7 of 16