Preliminary Technical Data

AD7265

ANALOG INPUT

The channels to be converted on simultaneously are selected via

the multiplexer address inputs A0 to A2. The logic states of

these pins are also checked upon the falling edge of CS and the

channels are chosen for the next conversion. The selected input

channels are decoded as shown in Table 6.

The analog inputs of the AD7265 may be configured as single

ended or true differential via the SGL/DIFF logic pin, as shown

in Figure 5. On the falling edge of CS, point A, the logic level of

the SGL/DIFF pin is checked to determine the configuration of

the analog input channels for the next conversion. If this pin is

tied to a logic low, the analog input channels to each on-chip

ADC are set up as three true differential pairs. If this pin is at a

logic high when CS goes low, the analog input channels to each

on-chip ADC are set up as six single-ended analog inputs. In

Figure 5 at point A, the SGL/DIFF pin is at a logic high so the

analog inputs are configured as single-ended for the next

conversion, i.e. sampling point B. At point B, the logic level of

the SGL/DIFF pin has changed to low; there fore, the analog

inputs are configured as differential for the next conversion

after this one, even though this current conversion is on single

ended configured inputs.

The analog input range of the AD7265 can be selected as 0 V to

made in a similar fashion to that of the SGL/DIFF pin by

checking the logic state of the RANGE pin upon the falling edge

of CS. The analog input range is set up for the next conversion.

If this pin is tied to a logic low upon the falling edge of CS, the

pin is tied to a logic high upon the falling edge of CS, the analog

OUTPUT CODING

The AD7265 output coding is set to either twos complement or

straight binary depending on which analog input configuration

is selected for a conversion. Table 5 shows which output coding

scheme is used for each possible analog input configuration.

A

CS

SCLK

SGL/DIFF

114

1

14

B

Table 5 AD7265 Output Coding

SGL/DIFF

Range

Output Coding

DIFF

Twos Complement

DIFF

Twos Complement

SGL

Straight Binary

SGL

Twos Complement

PSUEDO DIFF

Straight Binary

PSUEDO DIFF

Straight Binary

Figure 5. Selecting Differential or Single Ended Configuration

Table 6. Analog Input Type and Channel Selection

ADC A

ADC B

SGL/DIFF

A2

A1

A0

Comment

1

0

0

0

AGND

AGND

Single Ended

1

0

0

1

AGND

AGND

Single Ended

1

0

1

0

AGND

AGND

Single Ended

1

0

1

1

AGND

AGND

Single Ended

1

1

0

0

AGND

AGND

Single Ended

1

1

0

1

AGND

AGND

Single Ended

0

0

0

0

Fully Differential

0

0

0

1

Pseudodifferential

0

0

1

0

Fully Differential

0

0

1

1

Pseudodifferential

0

1

0

0

Fully Differential

0

1

0

1

Pseudodifferential

Rev. PrA | Page 11 of 16