LM9820CCWM datasheet(17/21 Pages) NSC

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Equation 6: Simplified output code calculation

1.8 Power Down Mode

Setting the Power Down (bit B0 of register 7) puts the device in a

low power standby mode. The analog sections are turned off to

conserve power. The digital logic will continue to operate if MCLK

continues, so for minimum power dissipation MCLK should be

stopped when the LM9810/20 enters the Power Down mode.

Recovery from Power Down typically takes 50µs (the time

required for the reference voltages to settle to 0.5 LSB accuracy).

2.0 Clamping

To perform a DC restore across the AC coupling capacitors at the

beginning of every line, the LM9810/20 implements a clamping

function. When NewLine is high and SampCLK is low, all three OS

inputs will be connected to either VREF+ or VREF-, depending on B4

of the Sampling and Color Mode register. If B4 is set to one (pos-

itive signal polarity), then the OS inputs will be connected to VREF-

. If B4 is set to zero (negative signal polarity), then they will be

connected to VREF+.

2.1 Clamp Capacitor Selection

This section explains how to select appropriate clamp capacitor

values.

The output signal of many sensors rides on a DC offset (greater

than 5V for many CCDs) which is incompatible with the

LM9810/20’s 5V operation. To eliminate this offset without resort-

ing to additional higher voltage components, the output of the

sensor is AC coupled to the LM9810/20 through a DC blocking

capacitor, CCLAMP. The sensor’s DOS output, if available, is not

used. The value of this capacitor is determined by the leakage

current of the LM9810/20’s OS input and the output impedance of

the sensor. The leakage through the OS input determines how

quickly the capacitor value will drift from the clamp value of VREF+

or VREF-, which then determines how many pixels can be pro-

cessed before the droop causes errors in the conversion (±0.1V

is the recommended limit for CDS operation). The output imped-

ance of the sensor determines how quickly the capacitor can be

charged to the clamp value during the black reference period at

the beginning of every line.

The minimum clamp capacitor value is determined by the maxi-

mum droop the LM9810/20 can tolerate while converting one

sensor line. The minimum clamp capacitor value is much smaller

for CDS mode applications than it is for CIS mode applications.

The LM9810/20 input leakage current is considerably less when

the LM9810/20 is operating in CDS mode. In CDS mode, the

LM9810/20 leakage current should be no more than 20nA. With

CDS disabled, which will likely be the case when CIS sensors are

used, the LM9810/20 leakage current can be as high as 25uA at

the maximum conversion rate.

2.1.1 CDS mode Minimum Clamp Capacitor Calculation:

The following equation takes the maximum leakage current into

the OS input, the maximum allowable droop, the number of pixels

on the sensor, and the pixel conversion rate, fSampCLK, and pro-

vides the minimum clamp capacitor value:

For example, if the OS input leakage current is 20nA worst-case,

the sensor has 2700 active pixels, the conversion rate is 2MHz

(tSampCLK = 500ns), and the max droop desired is 0.1V, the mini-

mum clamp capacitor value is:

2.1.2 CIS mode Minimum Clamp Capacitor Calculation:

If CDS is disabled, then the maximum LM9810/20 OS input leak-

age current can be calculated from:

where VSAT is the peak pixel signal swing of the CIS OS output

and CSAMP is the capacitance of the LM9810/20’s internal sam-

pling capacitor (2pF). Inserting this into Equation 7 results in:

with CSAMP equal to 2pF and VSAT equal to 2V (the LM9810/20’s

maximum input signal), then Equation 10 reduces to:

In CIS mode (CDS disabled), the max droop limit must be much

more carefully chosen, since any change in the clamp capacitor’s

DC value will affect the LM9810/20’s conversion results. If a

droop of one 10 bit LSB across a line is considered acceptable,

then the allowed droop voltage is calculated as: 2V/1024, or

OUT

INGB

DAC

()G

PGAC

DOS

SENSOR

CCLAMP

Figure 5: OS Clamp Capacitor and Internal Clamp

VREF+ or VREF-

LM9810/20

CLAMP MIN

---------dt

leakage current (A)

max droop(V)

---------------------------------------------------

number of pixels

SampCLK

--------------------------------------------

Equation 7: CDS mode CCLAMP MIN Calculation

CLAMP MIN

20nA

0.1V

--------------

2700

2MHz

---------------

270pF

Equation 8: CDS mode CCLAMP MIN Example

leakage

SA TfSampCLKCSAMP

Equation 9: CIS mode Input Leakage Current Calculation

CLAMP MIN

---------dt

SAT

SampCLK

--------------------------- C

SAMP

SampCLK

max droop(V)

------------------------------------ num pixels

Equation 10: CIS mode CCLAMP MIN Calculation

CLAMP MIN

4p(F)(V)

max droop(V)

------------------------------------ num pixels

Equation 11: CIS mode CCLAMP MIN Calculation

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