LM9820CCWM datasheet(8/21 Pages) NSC

8 / 21 page

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Pin Descriptions

Analog Power

This is the positive supply pin for the analog

supply. It should be connected to a voltage

source of +5V and bypassed to AGND with a

0.1µF monolithic capacitor in parallel with a

10µF tantalum capacitor.

AGND

This is the ground return for the analog sup-

ply.

Analog I/O

OSR, OSG, OSB,

Analog Inputs. These inputs (for Red,

Green, and Blue) should be tied to the sen-

sor’s OS (Output Signal) through DC block-

ing capacitors.

RefBypass

Internally generated reference voltage

bypass pin. It should be bypassed to AGND

through a .05uF monolithic capacitor.

VREF+, VREFMID,

VREF-

Voltage reference bypass pins. They should

each be bypassed to AGND through a .05uF

monolithic capacitor.

Input & Timing Control

MCLK

Master Clock. The ADC conversion rate will

be a maximum of ¼ of MCLK. Nominally

24MHz.

SampCLK

Sample Clock. SampCLK controls the con-

version rate of the ADC (up to ¼ of the

MCLK

rate) and sample timing. The signal

level is sampled while SampCLK is low and

held on the rising edge of SampCLK. When

CDS is enabled, the falling edge of SampCLK

causes the CCD reference level to be held.

If CDS is not enabled, VREF+ or VREF- is held

on the falling edge of SampCLK, depending

on the programmed signal polarity. SampCLK

is also used with NewLine to clamp the exter-

nal coupling capacitors.

NewLine

New Line signal. Used to indicate the start

of active pixels on a new line, to allow

clamping of the AC coupling caps, and to

allow programming of the configuration reg-

ister. When NewLine is high and SampCLK is

low, the OS inputs will be connected to

either VREF+ or VREF-. On the first rising edge

of MCLK after NewLine goes low, the internal

mux and the offset and gain settings will be

set to the appropriate values for the first

color of the next line set in the color mode

setting in the Sampler and Color Mode Reg-

ister. When NewLine is low, D[5-0] transmit

the pixel conversion data from the ADC.

When NewLine is high, D[5-0] enter TRI-

STATE and D2, D1 and D0 act as a serial

interface for programming the configuration

registers.

Digital Power

This is the positive supply pin for the digital

supply. It should be connected to a voltage

source of +5V and bypassed to DGND with a

0.1µF monolithic capacitor.

DGND

This is the ground return for the digital sup-

ply.

Digital I/O

-D0

Data Input/Output pins. When NewLine is

low, the 10 or 12 bit conversion results of

the ADC are multiplexed to D5-D0. When

NewLine

is high, the output drivers enter TRI-

STATE and D2, D1 & D0 act as a serial inter-

face for writing to the configuration regis-

ters.

LM9810

Output Mode

(NewLine Low)

MCLK0, MCLK1, MCLK2, MCLK3

b9,

b3,

b8,

b2,

b7,

b1,

b6,

b0,

b5,

b4,

LM9820

Output Mode

(NewLine Low)

MCLK0, MCLK1, MCLK2, MCLK3

b11,

b5,

b10,

b4,

b9,

b3,

b8,

b2,

b7,

b1,

b6,

b0,

Input Mode

(NewLine High)

-D3

Don’t Care

(SCLK)

Serial Data Clock.

(Latch)

Latch and shift enable signal. When

(Latch) is low, data is shifted into D0(SDI).

When D1(Latch) goes high, the last nine bits

shifted into D0(SDI) will be used to program

the addressed configuration register. To

avoid erroneous writes to the configuration

registers, D1(Latch) should be pulled low

when NewLine is high.

(SDI)

Serial input data. Data is valid on D2(SCLK)

rising edge. Three address bits followed by

six data bits (MSB first) should be shifted

into D0 before D1(Latch) goes high.

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