LM9820CCWM datasheet(7/21 Pages) NSC

7 / 21 page

http://www.national.com

Note 7: Two diodes clamp the OS analog inputs to

AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output

impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.

Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.

Note 9: Typicals are at TJ=TA=25°C, fMCLK = 24MHz, and represent most likely parametric norm.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the

ADC.

Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for

a white (full scale) image with respect to the reference level, VREF . VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum

correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the

LM9810/20 can correct for using its internal PGA.

Note 13:

PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula

where

Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and an offset

Note 15: The digital supply current (ID) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (

D5 - D0).

The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*

VD/tSampCLK where Nd is total number of data pins, Psw is the probability

of each data bit switching, CL is the capacitive loading on each data pin,

VD is the digital supply voltage and tSampCLK is the period of the SampCLK signal. Since Nd is

6, Psw should be .5, and

VD is nominally 5V, the switching current can usually be calculated from: Isw = 30*CL/tSampCLK. For example, if the capacitive load on each dig-

ital output pin (

D5 - D0) is 20pF and the period of tSampCLK is 1/6MHz or 167ns , then the digital switching current would be 7.2mA. The calculated digital switching current

will be drawn through the

VD pin and should be considered as part of the total power budget for he LM9810/20.

OS Input

AGND

TO INTERNAL

CIRCUITRY

VWHITE

VREF

VRFT

CCD Output Signal

Gain

PGA

----





PGA code

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