LM9820CCWM datasheet(15/21 Pages) NSC

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Applications Information

1.0 Programming the LM9810/20

1.1 Writing to the Configuration Register

When NewLine is high, D2, D1 & D0 act as a serial interface for writ-

ing to the configuration registers. D2 is the input serial clock

(SCLK), D0 is the input data pin (SDI), and D1 is the latch and

shift enable signal (Latch). When D1(Latch) is low, serial data is

shifted into D0(SDI), and must be valid on each rising edge of

(SCLK). Three register address bits followed by six data bits

should be shifted into D0(SDI), MSB first. When D1(Latch) transi-

tions from low to high, the last 6 data bits will be stored into the

configuration register addressed by the previous 3 address bits

(as shown in Diagram 3). D1(Latch) must remain high for at least

3 cycles of the serial clock on D2(SCLK) to write to the configura-

tion register.

1.2 CDS Mode

The LM9810/20 uses a high-performance CDS (Correlated Dou-

ble Sampling) circuit to remove many sources of noise and error

from the CCD signal. It also supports CIS image sensors with a

single sampling mode.

Figure 1 shows the output stage of a typical CCD and the result-

ing output waveform:

Figure 1: CDS

Capacitor C1 converts the electrons coming from the CCD’s shift

(Q2) buffers this voltage before it leaves the CCD. Q1 resets the

voltage across capacitor C1 between pixels at intervals 2 and 5.

When Q1 is on, the output signal (OS) is at its most positive volt-

age. After Q1 turns off (period 3), the OS level represents the

residual voltage across C1 (VRESIDUAL). VRESIDUAL includes

charge injection from Q1, thermal noise from the ON resistance

of Q1, and other sources of error. When the shift register clock

(Ø1) makes a low to high transition (period 4), the electrons from

the next pixel flow into C1. The charge across C1 now contains

the voltage proportional to the number of electrons plus VRESID-

UAL, an error term. If OS is sampled at the end of period 3 and

that voltage is subtracted from the OS at the end of period 4, the

VRESIDUAL term is canceled and the noise on the signal is

reduced ([VSIGNAL+VRESIDUAL]-VRESIDUAL = VSIGNAL). This is the

principal of Correlated Double Sampling.

If the LM9810/20 is programmed for correlated double sampling

(bit B5 of register 0 is cleared), then the falling edge of SampCLK

should occur toward the end of period 3 and the rising edge of

SampCLK

should occur towards the end of period 4. While Samp-

CLK

is high, the Reference level (VRESIDUAL) is sampled, and it is

held at the falling edge of SampCLK. While SampCLK is low, the sig-

nal level (VSIGNAL+ VRESIDUAL) is sampled and it is held at the ris-

ing edge of SampCLK. The output from the sampler is the potential

difference between the two samples, or VSIGNAL.

1.3 CIS Mode

The LM9810/20 supports CIS (Contact Image Sensor) devices by

offering a sampling mode for capturing positive going signals, as

opposed to the CCD’s negative going signal. The output signal of

a CIS sensor (Figure 2) differs from a CCD signal in two primary

ways: its output increases with increasing signal strength, and it

does not usually have a reference level as an integral part of the

output waveform of every pixel.

Figure 2: CIS

When the LM9810/20 is in CIS mode (Register 0, B5=1), it uses

either VREF+ or VREF- depending on the signal polarity setting (B4

of the Sampling and Color Mode register) as the reference (or

black) voltage for each pixel. If the signal polarity is set to one,

then VREF- will be held on the falling edge of SampCLK and the OS

signal will be held on the rising edge of SampCLK. If it is set to

zero, then VREF+ will be held on the falling edge of SampCLK and

the OS signal will be held on the rising edge of SampCLK. The ris-

ing edge of SampCLK should occur near the end of period 4, and

at least 50ns after the falling edge of SampCLK.

1.4 Multiplexer/Channel Switching

The offset and gain settings automatically switch after each ADC

conversion according to the color mode setting in the Sampler

and Color Mode register (register 0). For example, if the color

mode (bits B2,B1 & B0) is set to 001, the offset and gain will alter-

nately switch between the R, G and B settings after each conver-

sion. The input multiplexer never changes during a line, but if the

color mode is set to Line Rate Color (000), the mux will automati-

cally switch after each new line.

The offset and gain settings will always start with the first channel

of the programmed mode after a falling edge on NewLine. For

RS (RESET)

(from shift register)

VDD

VSS

Ø1

SampCLK

OS (CCD)

OS (CIS)

SampCLK

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