LM9820CCWM datasheet(6/21 Pages) NSC

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,

but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND=

AGND=DGND=0V, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN<GND or VIN>VA or VD), the current at that pin should be limited to 25mA. The 50mA

maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, ΘJA and the ambient temperature, TA. The maximum allow-

able power dissipation at any temperature is PD = (TJmax - TA) / ΘJA. TJmax = 150°C for this device. The typical thermal resistance (ΘJA) of this part when board mounted

is 84°C/W for the M20B SOIC package

Note 5: Human body model, 100pF capacitor discharged through a 1.5k

Ω resistor.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear

Data Book for other methods of soldering surface mount devices.

AC Electrical Characteristics

The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, tMCLK=1/fMCLK, tr=tf=5ns, Rs=25Ω. Boldface

limits apply for T

A=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)

Symbol

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

MCLK

Maximum MCLK Frequency

MHz (min)

MCLK

Duty Cycle

% (min)

% (max)

tMCLK

MCLK

period

ns (min)

tSCNL

SampCLK

falling edge before NewLine

falling edge

tMCLK(min)

tSampCLK

SampCLK

period

tMCLK(min)

tSampLo

Low time for SampCLK

ns (min)

tSampHi

High time for SampCLK

ns (min)

tSampSU

SampCLK

falling edge before rising

edge of MCLK

ns (min)

tDDO

falling edge of MCLK before new valid

data

ns (max)

tHDO

hold time of current data from falling

edge of MCLK

ns (min)

tSCLK

(SCLK) Serial Clock Period

tMCLK(min)

tDSU

Input data setup time before

(SCLK) rising edge

ns (min)

tDH

Input data hold time after D2(SCLK)

rising edge

ns (min)

tSCLKLA

(SCLK) rising edge after bit B0

before D1(Latch) rising edge

ns (min)

tLASCLK

(Latch) rising edge before next

(SCLK) rising edge

ns (min)

tLA

High time for D1(Latch)

tMCLK (min)

tLANL

(Latch) rising edge before NewLine

falling edge

tSampCLK

(min)

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