16

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Diagram 17: Digital Data Timing, output data and coefficient data on same buses, one clock

(GCLK) for coefficient data, GCLK generated by LM9812.

EOC = RD PIXEL

EXTERNAL DATABUS

D0-D9

CD0-CD9

GCLK (from LM9812)

Diagram 18: Digital Data Timing, output data and coefficient data on separate buses, two clocks (OCLK and

GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 0°, RD PIXEL held low.

EOC

CD0-CD9

GCLK (to LM9812)

OCLK (to LM9812)

D0-D9

Diagram 19: Digital Data Timing, output data and coefficient data on separate buses, two clocks (OCLK and

GCLK) for coefficient data, OCLK and GCLK input to LM9812, OCLK and GLCK phase = 180°, RD PIXEL held low.

EOC

CD0-CD9

GCLK (to LM9812)

OCLK (to LM9812)

D0-D9