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LM9812 датащи(PDF) 6 Page - National Semiconductor (TI) |
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LM9812 датащи(HTML) 6 Page - National Semiconductor (TI) |
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6 / 37 page ![]() 6 http://www.national.com tWR HOLD D0-D9 data valid after rising edge of WR (hold time) 0 ns (min) AC Electrical Characteristics, MCLK Dependent The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz, tMCLK=1/fMCLK, tr=tf=5ns, Rs=25Ω, CL (databus loading) = 50pF/pin. Refer to Table 2: Configuration Register Parameters for limits labeled C.R. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) tR/S START Rising edge of RUN/STOP to Rising edge of SYNC SYNC OUT mode 16 MCLKs (max) tSTART Rising edge of SYNC to rising edge of TR1 SYNC IN mode SYNC IN mode SYNC OUT mode 1+tGUARDBAND 13+tGUARDBAND tGUARDBAND tGUARDBAND 14+tGUARDBAND tGUARDBAND MCLKs (min) MCLKs (max) MCLKs tSYNC END Falling edge of SYNC to last rising edge of EOC SYNC IN mode SYNC OUT mode 8 0 9 0 MCLKs (max) MCLKs (max) tSYNC LOW SYNC low time SYNC IN mode SYNC OUT mode 8 # of EOL PIxels - 4 MCLKs (min) Pixel periods tTR1 WIDTH, tTR2 WIDTH TR1, TR2 Transfer Pulse Width C.R. MCLKs tGUARD TR1, TR2 Transfer Pulse Guardband C.R. MCLKs tRS WIDTH Reset Pulse Width C.R. MCLKs tCLAMP ON Start of Optical Black clamping period C.R. MCLKs tCLAMP OFF End of Optical Black clamping period C.R. MCLKs tØ Ø1, Ø2 clock period Standard Mode Even/Odd Mode 12 24 MCLKs MCLKs tRS RS pulse position from Ø1 edge C.R. MCLKs tHOLD REF Reference hold (sample) position from RS edge C.R. MCLKs tHOLD SIG Signal hold (sample) position from RS edge C.R. MCLKs tOCLK LOW OCLK low time (OCLK as Output) 2 bus mode 1bus mode 2*tMCLK 1*tMCLK ns tOCLK HIGH OCLK high time (OCLK as Output) 2 bus mode 1 bus mode 2*tMCLK 3*tMCLK ns tGCLK LOW GCLK low time (GCLK as Output) 2 bus mode 1 bus mode 2*tMCLK 1*tMCLK ns tGCLK HIGH GCLK high time (GCLK as Output) 2 bus mode 1 bus mode 2*tMCLK 3*tMCLK ns AC Electrical Characteristics, MCLK Independent (Continued) The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz, tMCLK=1/fMCLK, tr=tf=5ns, Rs=25¾, CL (databus loading) = 50pF/pin. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) |
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