LM9812 datasheet(9/37 Pages) NSC

9 / 37 page

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Pin Descriptions

Sensor Driver Signals

ø1

Digital Output. Clock signal, phase 1.

ø2

Digital Output. Clock signal, phase 2.

Digital Output. Reset pulse.

TR1, TR2

Digital Output. Transfer pulses.

Analog I/O

OSR, OSG,

OSB,

Analog Inputs. These inputs (for Red, Green,

and Blue) should be tied to the sensor’s OS

(Output Signal) through DC blocking capaci-

tors.

VREF IN

Analog Input. This is the system reference volt-

age input and should be connected to a 2.0V

voltage source and bypassed to AGND with a

0.05µF monolithic capacitor.

VREF LO OUT,

VREF LO IN

Analog Output/Input. VREF LO OUT is a voltage

equal to 0.49VA - VREF IN/2 (1.45V for VREF

IN=2V) developed by the LM9812. It should be

tied to VREF LO IN and bypassed to AGND with

a 0.05µF monolithic capacitor.

VREF MID OUT,

VREF MID IN

Analog Output/Input. VREF MID OUT is a voltage

equal to 0.49VA (2.45V for VREF IN=2V) devel-

oped by the LM9812. It should be tied to VREF

MID IN and bypassed to AGND with a 0.05µF

monolithic capacitor.

VREF HI OUT,

VREF HI IN

Analog Output/Input. VREF HI OUT is a voltage

equal to 0.49VA + VREF IN/2 (3.45V for VREF

IN=2V) developed by the LM9812. It should be

tied to VREF HI IN and bypassed to AGND with a

0.05µF monolithic capacitor.

Configuration Register I/O

Digital Input. This is the Chip Select signal for

reading or writing to the Configuration Register

through the D0-D9 databus. This input must be

low in order to enable writing to or reading from

the Configuration Register.

Digital Input. A low signal on this input, when

SYNC and CS are also low, places the data in

the currently addressed Configuration Regis-

ter on the D0-D9 databus. A RD cycle also

resets the internal address latching state

machine. NOTE: If this pin is taken low when

CS is high, the D0-D9 databus will come out of

tri-state and drive random data onto the bus.

Digital Input. This input, when simultaneously

asserted along with CS, transfers the data on

the D0-D9 databus to the LM9812. If this is the

first write in the cycle, this data is the address

to be read or written to. If this is the second

write in the cycle, this data is the data to be

written to the Configuration Register at the cur-

rently latched address. Writing to the Configu-

ration Register is independent of the state of

SYNC.

General Digital I/O

MCLK

Digital Input. This is the 24MHz (typical) master

system clock.

SYNC

Digital Input (SYNC_IN mode) /

Digital Output (SYNC_OUT mode).

In the SYNC_IN mode, a low-to-high transition

on this input begins a line scan operation. The

line scan operation terminates when SYNC is

taken low. In the SYNC_OUT mode, the rising

edge of this output indicates the start of a line

of data and the falling edge indicates the end of

a line of data.

RUN/STOP

Digital Input. In the SYNC_OUT mode, this

input should be taken high to begin converting

a series of lines, and taken low to stop convert-

ing a series of lines. In the SYNC_IN mode this

input is ignored.

Digital Coefficient I/O

CD0 (LSB) -

CD9 (MSB)

Digital Inputs. This is the 10 bit data path for

the pixel-rate gain coefficient and offset data.

OCLK

Digital Input/Output. This is the signal that is

used to clock the Offset coefficients into the

LM9812 through the CD0-CD9 databus. This

can be either an output or an input depending

on the state of bit 7 of Register 9. Data is

latched on the rising edge of OCLK.

GCLK

Digital Input/Output. This is the signal that is

used to clock the Shading (gain) coefficients

into the LM9812 through the CD0-CD9 data-

bus. This can be either an output or an input

depending on the state of bit 7 of Register 9.

Data is latched on the rising edge of GCLK.

Digital Output I/O

D0 (LSB)-

D9 (MSB)

Digital Inputs/Outputs. When SYNC is high and

RD PIXEL is low, this data bus outputs the 10

bit digital output data during line scan. This

databus is also used for reading or writing to

the Configuration Register using the RD, WR

and CS signals. Writing to the Configuration

the Configuration Register can only occur

when SYNC is low.

EOC

Digital Output. This is the End Of Conversion

signal from the LM9812 indicating that new

pixel data is available on the D0-D9 databus.

RD PIXEL

Digital Input. When SYNC is high, taking this

input low places the digital pixel data stored in

the output latch onto the D0-D9 bus. This input

is ignored when SYNC is low.

Test

TEST

Analog Output. This pin can be used to view

the CDS and Clamp signals. See Register 27,

bits 6 and 7.

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