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1.4.2 RS

The LM9812 also generates the RS (reset) pulse required to

clear the CCD’s output capacitor of the previous pixel’s charge.

The RS pulse’s width and position (relative to the edge of the ø1

pulse) is determined by the value in Configuration Register 21.

See Diagrams 10 and 12. The polarity of the RS pulse is deter-

mined by Register 26, bit 1. If not needed, this pulse can be dis-

abled by setting Register 25, bit 2 to a 1.

1.4.3 ø1 and ø2

ø1 and ø2 are the two phase clock for the CCD shift register. ø2

is always the inverse of ø1. For “standard” CCDs, the ø1 and ø2

frequency is equal to the pixel rate, the same frequency as the

RS pulse. In Standard Mode, the RS pulse position and Sample

Reference/Sample Signal edges are set with respect to the falling

edge of ø1. For “even/odd” CCDs, the ø1 and ø2 frequency is

equal to one half the pixel rate, a pixels is sampled after both the

rising and falling edges of the ø clock. In Even/Odd Mode, the RS

pulse position and Sample Reference/Sample Signal edges are

set with respect to the either edge of ø1. Standard or Even/Odd

mode is selected by setting bit 0 of Register 24. The absolute

polarity of the ø pulses is determined by Register 26, bits 0 and 4

(both bits perform the same function). If not needed, one or both

ø pulses can be disabled by setting Register 25, bits 0 and 1 to

the appropriate value.

1.5 DIGITAL INTERFACE

There are three main sections to the digital interface of the

LM9812: the Configuration Register interface (through which all

device programming is done), the Correction Coefficient Data

interface (the 10 bit-wide input databus for gain and offset correc-

tion coefficients), and the 10 bit-wide Pixel Data output databus

(where the corrected digital output data appears).

1.5.1 Configuration Register I/O

The Configuration Register is written to and read from through

the D0-D9 databus, using the CS, WR, and RD signals. To write

to the Configuration Register, follow the timing shown in Diagram

24. The first byte is the address of the Configuration Register to

be written to, the second byte is the data to be stored at that

address. Configuration Register writes can occur at any time,

independent of the state of the SYNC pin.

To read from the Configuration Register, follow the timing shown

in Diagram 25. The first byte is the address of the Configuration

address. The SYNC pin must be low in order to read from the

Configuration Register. To ensure that SYNC is low when in the

SYNC out mode, RUN/STOP must be low until the end of the

active pixels.

If the LM9812’s RD pin is taken low,

even if the CS pin is high, the

D0-D9 databus will be driven. Never take the RD pin low unless

you are actually doing a Configuration Register read.

1.5.2 Pixel Data I/O

The output of the multiplier is available on the D0-D9 databus. If

the Data Read Phase bit (bit 5 of Register 26) is set to a 0, Data

changes shortly before the falling edge of EOC and remains valid

for tDATAVALID. If the Data Read Phase bit is set to a 1, Data

changes shortly before the rising edge of EOC and remains valid

for tDATAVALID. The D0-D9 databus comes out of tri-state when

SYNC is high and RD PIXEL is low. If SYNC is low, RD PIXEL will

have no effect.

When reading pixel data, RD PIXEL may be driven by EOC, put-

ting the data on the bus only when EOC is low, and allowing other

data on the bus (such as CD0-CD9 correction data) at other

times. In this way the output data and correction coefficient data

can share the same databus (See Diagrams 16, 17, 20, and 21).

1.5.3 Correction Coefficient Data I/O

Coefficient data for the pixel rate Offset Subtractor and Shading

Multiplier enters the LM9812 through the CD0-CD9 databus. To

maximize flexibility for the system designer, there are several

clocking options available in this mode: separate or combined

buses for the CD0-CD9 and the D0-D9 data, one (GLCK) or two

(GLCK and OCLK) clock signals to latch the Correction Coeffi-

cient data, and the option to have the LM9812 generate the clock

signals or have them supplied to the LM9812. Timing for these

different options is shown in Diagrams 14 through 21, and

described below.

Diagram 14 shows the case where the correction data (CD0-

CD9) is on a separate bus from the output data (D0-D9) (Register

9, bit 4=0). The GLCK and OCLK signals are generated by the

LM9812 (Register 9, bit 5=0, bit 7=1). Gain correction data is

latched on the rising edge of GCLK, and offset correction data is

latched on the rising edge of OCLK. There is a one EOC clock

latency between the latching of the gain coefficient for a particular

pixel and the output of that pixel on the D0-D9 databus.

Diagram 15 shows the case where the correction data (CD0-

CD9) is on a separate bus from the output data (D0-D9) (Register

9, bit 4=0). The LM9812 generates the GCLK signal only (Regis-

ter 9, bit 5=1, bit 7=1). Gain correction data is latched on the ris-

ing edge of GCLK, and offset correction data is latched on the

falling edge of GCLK. There is a one EOC clock latency between

the latching of the gain coefficient for a particular pixel and the

output of that pixel on the D0-D9 databus.

Diagram 16 shows the case where the correction data (CD0-

CD9) is on the same bus as the output data (D0-D9) (Register 9,

bit 4=1). The GLCK and OCLK signals are generated by the

LM9812 (Register 9, bit 5=0, bit 7=1). Gain correction data is

latched on the rising edge of GCLK, and offset correction data is

latched on the rising edge of OCLK. Using the EOC output to

control the RD PIXEL input allows the CD0-CD9 and the D0-D9

data to exist on the same bus with no contention. There is a one

CD0-CD9 tied to

D0-D9

(1 bus)

CD0-CD9

separate from

D0-D9

(2 bus)

GLCK, OCLK are

outputs (2 Clock)

Diagram 16

Diagram 14

GLCK is output

(1 Clock)

Diagram 17

Diagram 15

GLCK, OCLK are

inputs

Diagrams 20, 21

Diagrams 18, 19

Table 3:Correction Databus Options

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