WM8753LEBSLASHV datasheet(70/87 Pages) WOLFSON

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Advanced Information

WM8753L

AI Rev 3.1 June 2004

HIFI DAC + VOICE CODEC MODE

In this mode the stereo ADC and voice DAC are used for voice record and playback and the

HiFi DAC is used for high quality playback. The HiFi DAC may be powered off for voice codec

only operation. In this mode the sample rate for the HiFi DAC is controlled using SR[4:0] and

USB, as detailed in the HIFI Codec Mode section above. The Voice DAC and ADC sample rate

is controlled by PSR. In this mode the Voice DAC and ADC sample rate is derived from the

master clock selected for the voice DAC and ADC (see

Figure 26). The Voice codec and HiFi DAC may operate at different sample rates from the

same or separate master clocks. e.g. for HiFI DAC operation at fs=48kHz and voice codec

operation at fs=8kHz with mclk = 12.288MHz. PCMDIV (reg52) should be set to divide mclk by

6 to provide a 2.048Mhz (= 256 x 8kHz) clock for the voice DAC and ADC.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

SRMODE

ADC Sample rate mode

0 – ADC sample rate selected

by SR[4:0] and USB

1 – ADC sample rate selected

by PSR[1:0]

R6 (06h)

Sample Rate

Control

PSR

Voice

Codec

Sample

Rate

Control

0 – 256fs mode

1 – 384fs mode

Table 68 Clocking and Sample Rate Control

The clocking of the WM8753L voice codec is controlled using the PSR control bits. If MCLK changes,

the sample rates change proportionately.

POWER SUPPLIES

The WM8753L can use up to four separate power supplies:

AVDD and AGND: Analogue supply, powers all analogue functions except the headphone

drivers. AVDD can range from 1.8V to 3.6V and has the most significant impact on overall

power consumption (except for power consumed in the headphone). A large AVDD slightly

improves audio quality.

HPVDD, SPKRVDD and HP/SPKRGND: Headphone and Speaker supplies, power the

headphone and speaker drivers. HPVDD and SPKRVDD can range from 1.8V to 3.6V. HPVDD

and SPKRVDD are normally tied to AVDD, but it requires separate layout and decoupling

capacitors to curb harmonic distortion. With a larger HPVDD and SPKRVDD, louder headphone

and speaker outputs can be achieved with lower distortion. If HPVDD and /or SPKRVDD are

lower than AVDD, the output signal may be clipped.

PLLVDD and PLLGND. PLL supplies, power the two on-chip PLLs. PLLVDD can range from

1.8V to 3.6V.

DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.

DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The return path for

DCVDD is DGND, which is shared with DBVDD.

DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it

possible to run the digital core at very low voltages, saving power, while interfacing to other

digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has

no effect on audio quality. DBVDD can range from 1.8V to 3.6V. The return path for DBVDD is

DGND, which is shared with DCVDD.

It is possible to use the same supply voltage on all four. However, digital and analogue supplies

should be routed and decoupled separately to keep digital switching noise out of the analogue signal

paths.

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