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WM8753LEB/V датащи(PDF) 66 Page - Wolfson Microelectronics plc

номер детали WM8753LEB/V
подробное описание детали  HI FI AND TELEPHONY DUAL CODEC
PDF  87 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8753LEB/V датащи(HTML) 66 Page - Wolfson Microelectronics plc

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Advanced Information
WM8753L
w
AI Rev 3.1 June 2004
66
5
CLK1SEL
0
CLKOUT1 select
0 : from MCLK pin
1 : from PLL1
4
CLK1DIV2
0
CLKOUT1 Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
3
MCLK1DIV2
0
MCLK Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
2
PLL1DIV2
0
PLL1 Output Divide by 2
0 : Divide disabled
1 : Divide enabled
1
PLL1RB
1
PLL1 reset
0 : PLL reset
1 : PLL active
R53 (35h)
PLL1
Control (1)
0
PLL1EN
0
PLL 1 Enable
0 : Disabled
1 : Enabled
5
CLK2SEL
0
CLKOUT2 select
0 : from MCLK pin
1 : from PLL2
4
CLK2DIV2
0
CLKOUT1 Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
3
MCLK2DIV2
0
MCLK Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
2
PLL2DIV2
0
PLL2 Output Divide by 2
0 : Divide disabled
1 : Divide enabled
1
PLL2RB
1
PLL2 reset
0 : PLL reset
1 : PLL active
R57 (39h)
PLL2
Control (1)
0
PLL2EN
0
PLL2 Enable
0 : Disabled
1 : Enabled
Table 62 PLL and Clocking Control
The PLL frequency ratio R = f2/f1 (see
Figure 26 ) can be set using K and N:
N = int R
K = int (2
22 (R-N))
Example:
mclk=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < N < 13. There is a divide by 4 and a selectable divide by 2 after the
PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f2 = 8 x
12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
N = int R = 8
k = int ( 2
22 x (8.192 – 8)) = 805306 = C49BAh



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