WM8737 datasheet(28/38 Pages) WOLFSON

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WM8737L

Preliminary Technical Data

AI Rev 3.0 May 2004

MASTER CLOCK AND AUDIO SAMPLE RATES

The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The

WM8737L supports a wide range of master clock frequencies, and can generate many commonly

used audio sample rates directly from the master clock.

There are two clocking modes:

•

‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples

•

USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in

systems with a USB interface, and eliminates the need for an external PLL to generate

another clock frequency for the audio ADC.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKDIV2

Master Clock Divide by 2

1: MCLK is divided by 2

0: MCLK is not divided

USB

Clocking Mode Select

1: USB Mode

0: ‘Normal’ Mode

5:1

SR[4:0]

0000

Sample Rate Control

R8 (08h)

Clocking and

Sample Rate

Control

AUTO

DETECT

Clock Ratio Autodetect

(Slave Mode Only)

0: Autodetect Off

1: Autodetect On

Table 15 Clocking and Sample Rate Control

The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the

CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.

Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital

filter chacteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital

Filter Characteristics).

Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of

MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates

(e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small

amount. This is not audible, as the maximum deviation is only 0.27% (8.0214kHz instead of 8kHz in

USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).

In slave mode, it is possible to autodetect the audio clock rate ratio, instead of programming it. The

WM8737L can autodetect the following clock ratios:

•

CLKDIV2 = 0: MCLK = 128fs, 192fs, 256fs, or 384fs subject to MCLK < 40MHz

•

CLKDIV2 = 1: MCLK = 256fs, 384fs, 512fs, 768fs, 1024fs, 1536fs, subject to MCLK <

40MHz

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