WM8737 datasheet(17/38 Pages) WOLFSON

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Preliminary Technical Data

WM8737L

AI Rev 3.0 May 2004

MICROPHONE BIAS

The MICBIAS output provides a low noise reference voltage suitable for biasing electret type

microphones and the associated external resistor biasing network. The output voltage is derived from

VREF and is programmable in three steps from 0.75

× AVDD to 1.2 × AVDD, as shown below.

Supply voltage MVDD must be at least 170mV higher than the desired MICBIAS voltage to ensure

correct MICBIAS operation.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Power

Management

1:0

MICBIAS[1:0]

Microphone Bias Control

00: MICBIAS OFF (powered down,

high-impedance output)

01: VMICBIAS = 0.75

× AVDD

10: VMICBIAS = 0.9

× AVDD

11: VMICBIAS = 1.2

× AVDD

Table 6 MICBIAS Control

The internal MICBIAS circuitry is shown below. MVDD is a separate power supply pin used only for

MICBIAS and the microphone preamplifiers. When MICBIAS < AVDD, then MVDD can be tied to

AVDD. However, when MICBIAS = 1.2

× AVDD, then MVDD must be large enough to generate this

output voltage, i.e. it must be higher than AVDD.

Note: The maximum voltage for MVDD of 3.6V must be observed.

AGND

MICBIAS

VREF

internal

resistor

MVDD

Figure 6 Microphone Bias Schematic

Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors

therefore must be large enough to limit the MICBIAS current to 3mA. Please refer to the

“Applications Information” section for recommended external components.

PGA CONTROL

The Left and Right PGAs match the input signal levels to the ADC input ranges. The PGA gain is

logarithmically adjustable from –97dB to +30dB in 0.5dB steps. Each PGA can be controlled either

by the user or by the ALC function (see “Automatic Level Control” section). When ALC is enabled for

one or both channels then writing to the corresponding PGA gain control register has no effect. The

gain is independently adjustable on both Right and Left Line Inputs. By setting the LVU or RVU bits

whilst programming the PGA gain, both channels can be simultaneously updated. The inputs can

also be muted under software control. The PGA control register maps are shown in Table 7 PGA

Software Control.

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