AD9528BCPZ datasheet(29/68 Pages) AD

29 / 68 page

AD9528

Data Sheet

Rev. C | Page 28 of 67

Figure 30. PLL2 Block Diagram

PLL2 Input 2× Frequency Multiplier

The 2× frequency multiplier provides the option to double the

frequency at the PLL2 reference input. A higher frequency at

the input to the PLL2 (PFD) allows reduced in-band phase

noise and greater separation between the frequency generated

by the PLL and the modulation spur associated with the PFD.

Note that, as the input duty cycle deviates from 50%, harmonic

distortion may increase. As such, beneficial use of the frequency

multiplier is application specific. Typically, a VCXO with proper

interfacing has a duty cycle that is approximately 50% at the

VCXO_IN inputs. Note that the maximum output frequency of

the 2× frequency multipliers must not exceed the maximum

PFD rate specified in Table 7.

If the 2× frequency multiplier is used, a fixed phase offset can

occur from power-up to power-up between the input to the 2×

frequency multiplier and the PLL2 PFD reference input. This

presents the possibility for a fixed phase offset between the

VCXO_IN frequency and PLL2 output of ½ the period of the

signal applied to the VCXO_IN and VCXO_IN pins. If the

internal SYSREF generator is used, choose the PLL2 feedback

path as the input signal of the SYSREF generator to ensure fixed

phase alignment of the SYSREF generator from power-up to

power-up.

PLL2 Input Reference Divider

The input reference divider (R1) provides division in integer

steps from 1 to 31 with a maximum input frequency of 275 MHz.

The divider provides an option to prescale the PFD rate of PLL2

for output frequency planning and to accommodate more

flexibility for setting the desired loop bandwidth for PLL2.

If the R1 divider is used along with the SYSREF generator,

choose the PLL2 feedback path as the input signal of the

SYSREF generator to ensure fixed phase alignment of the

SYSREF generator from power-up to power-up.

PLL2 Feedback Dividers

PLL2 has two feedback paths as shown in Figure 30. In normal

PLL2 operation mode, the PLL2 feedback path consists of N2

(an 8-bit divider) and M1 (a VCO RF divider). The product of

N2 and M1 establishes the total PLL multiplication value for

PLL2.

The second feedback path for PLL2 uses the VCO CAL divider

(see Figure 30). The VCO CAL divider is exclusively used to

calibrate the internal VCO of PLL2. Register 0x0201,

the PLL multiplication values for both PLL2 feedback paths.

The total PLL multiplication in both feedback paths must equal

one another for proper VCO calibration. After each VCO

calibration, the VCO CAL divider feedback path automatically

disables and reverts back to the feedback path with N2 and M1

dividers for normal operation. The VCO CAL divider is not

available outside of VCO calibration.

The VCO CAL divider consists of a prescaler (P) divider and

two counters, A and B. The total divider value is

VCO CAL divider = (P × B) + A

where P = 4.

The VCO CAL feedback divider has a dual modulus prescaler

architecture with a nonprogrammable P that is equal to 4. The

value of the B counter can be from 3 to 63, and the value of the

A counter can be from 0 to 3. 16 is the minimum supported

divide value.

The VCO RF divider (M1) provides frequency division between

the internal VCO and the clock distribution. The VCO RF divider

can be set to divide by 3, 4, or 5. The VCO RF divider is part of

the total PLL2 feedback path value for normal operation.

PLL2 Loop Filter

The PLL2 loop filter requires the connection of an external

capacitor from LF2_CAP (Pin 14) to LDO_VCO (Pin 15). The

VCO CAL DIVIDER

TO DIST/

RESYNC

×2

LDO

PLL_1.8V

VDD

LDO_VCO

DIVIDE-BY-

1, 2, 3...31

RF VCO

DIVIDER

÷3, ÷4, ÷5

DIVIDE-BY-4

PRESCALER

A/B

COUNTERS

N = 1 TO 256

CHARGE PUMP

8 BITS, 3.5µA LSB

PFD

RZERO

RPOLE2

CPOLE1

CPOLE2

LF2_CAP

AD9528

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