AD9528BCPZ datasheet(58/68 Pages) AD

58 / 68 page

Data Sheet

AD9528

Rev. C | Page 57 of 67

Bits

Bit Name

Description

[4:2]

Reserved

[1:0]

PLL2 charge pump mode

Controls the mode of the PLL2 charge pump.

00 = tristate.

01 = pump down.

10 = pump up.

11 (default) = normal.

Table 51. PLL2 VCO Control (Register 0x0203)

Bits

Bit Name

Description

[7:5]

Reserved

Reserved.

Doubler and R1 divider path enable

0 (default) = bypasses doubler and R1 divider path to PLL2 frequency detector.

1 = enables doubler and R1 divider path.

Reset VCO calibration dividers

0 (default) = normal operation.

1 = resets A and B dividers.

Treat reference as valid

0 (default) = uses the PLL1 VCXO indicator to determine when the reference clock to the

PLL2 is valid.

1 = treats the reference clock as valid even if PLL1 does not consider it to be valid.

Force VCO to midpoint frequency

Selects VCO control voltage functionality.

0 (default) = normal VCO operation.

1 = forces VCO control voltage to midscale.

Manual VCO calibrate (not

autoclearing)

1 = initiates VCO calibration (this is not an autoclearing bit).

0 = resets the VCO calibration.

Table 52. PLL2 RF VCO Divider (M1) (Register 0x0204)

Bits

Bit Name

Description

[7:6]

Reserved

Reserved.

PFD reference edge

select

1 = falling edge.

0 = rising edge.

PFD feedback edge

select

1 = falling edge.

0 = rising edge.

RF VCO divider (M1)

power-down

1 = powers down the M1 divider.

0 = normal operation.

[2:0]

RF VCO divider (M1),

Bits[2:0]

Bit 2

Bit 1

Bit 0

Divider Value

Divide by 3.

Divide by 4.

Divide by 5.

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