AD9528BCPZ datasheet(35/68 Pages) AD

35 / 68 page

AD9528

Data Sheet

Rev. C | Page 34 of 67

SYSREF GENERATOR

The SYSREF pattern generator produces a user defined SYSREF

signal (see Table 23). The input clock to the pattern generator is

provided by the signal originating at the VCXO_IN

and VCXO_IN pins, or with the signal at the feedback node of

PLL2. The pattern generator contains a fixed divide by 2

followed by a programmable 16-bit K divider (set by

width of the SYSREF. The value of K ranges from 0 to 65535.

For example, if the pattern generator input clock is 122.88 MHz,

the maximum SYSREF period is 131,070/122,880,000 seconds

(1066 μs). The pattern generator acts as a timer that only issues

pulses synchronous to all other outputs, regardless of when an

asynchronous SYSREF request is issued.

SYSREF Request

The SYSREF request signal starts or stops the internal SYSREF

pattern generator. The signal is controlled by software or via pin

control. The SYSREF request method is controlled by

Software Control

In software control mode, the SYSREF pattern generator is

always level trigger sensitive to the SYSREF pattern generator

trigger control bits (Register 0x402, Bits[6:5]). With Bit 6 = 0 for

level trigger mode, Bit 5 is used as the trigger. If N-shot mode is

enabled, set Bit 5 = 1 from 0 to start the SYSREF pattern sequence.

After the sequence is complete and N pulses are output, the

SYSREF pattern generator automatically clears Bit 5 and waits

for the next SYSREF request.

In continuous mode, the pattern sequence continues if Bit 5 = 1.

Clear Bit 5 to stop the sequence and wait for the next SYSREF

request.

Pin Control—Level Trigger Mode

In level trigger mode (Register 0x0402, Bit 6 = 0), the SYSREF

pattern generator is controlled by the SYSREF_REQ pin. If N-

shot mode is enabled, force the SYSREF_REQ pin to 1 from 0 to

start the SYSREF pattern sequence. After the sequence is complete

and N pulses are output, force the SYSREF_REQ pin to 0. The

pattern generator then waits for the next SYSREF request.

In continuous mode, force the SYSREF_REQ pin to 1 from 0 to

start the SYSREF pattern sequence. Force the SYSREF_REQ pin

to 0 to stop the sequence. The pattern generator then waits for

next SYSREF request.

Pin Control—Edge Trigger Mode

In edge trigger mode, the SYSREF pattern generator is controlled

by the rising edge or falling edge on the SYSREF_REQ pin. The

rising or falling active edge is determined by Register 0x0402,

Bits[6:5]. With Bit 6 = 1, Bit 5 controls the active trigger edge. If

N-shot mode is enabled, the SYSREF_REQ pin active edge starts

the SYSREF pattern sequence. After the sequence is complete and

N pulses are output, the pattern generator waits for the next

SYSREF request. If SYSREF_REQ is set to 0 before N pulse(s)

are done, the current pattern sequence is not affected. Therefore, if

the new SYSREF_REQ active edge arrives before the pattern

sequence is complete, the new request is missed.

In continuous mode, the SYSREF_REQ active edge starts the

SYSREF pattern sequence. After the sequence, the pattern

generator waits for the next SYSREF request.

Table 23. On-Chip SYSREF Generation Modes

SYSREF Pattern

Generator Mode

(Register 0x0403,

Bits[5:4])

Generation Output Mode

Description

N-shot mode (Register 0x0403, Bits[3:1])

The SYSREF outputs N pulses after the SYSREF request is initiated

and then the SYSREF output goes logic low until the next SYSREF

request. N can be programmed as 1, 2, 4, 6, or 8.

N-shot mode[2:0] = 001 = 1 pulse out

N-shot mode[2:0] = 010 = 2 pulses out

N-shot mode[2:0] = 011 = 4 pulses out

N-shot mode[2:0] = 100 = 6 pulses out

N-shot mode[2:0] = 101 = 8 pulses out

N-shot mode[2:0] = 110 or greater = 1 pulse out

Continuous mode

The SYSREF output continuously outputs a 101010…pulse train

and behaves like a clock with a frequency of f

IN/(2 × K) after the

SYSREF request is initiated.

PRBS

Not applicable.

Stop

In stop mode, the SYSREF output is static low.

AD9528BCPZ датащи(PDF) 35 Page - Analog Devices

AD9528BCPZ датащи(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

датащи скачать

ссылки URL