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AD9528BCPZ датащи(PDF) 27 Page - Analog Devices

номер детали AD9528BCPZ
подробное описание детали  Maximum output frequency
PDF  68 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9528BCPZ датащи(HTML) 27 Page - Analog Devices

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AD9528
Data Sheet
Rev. C | Page 26 of 67
PLL1 has the flexibility to operate with a narrow loop bandwidth.
This relatively narrow loop bandwidth gives the AD9528 the
ability to suppress jitter that appears on the input references
(REFA and REFB). The low phase noise output of PLL1 acts as
the reference to PLL2 and can be routed to the clock
distribution section.
PLL1 Reference Clock Inputs
The AD9528 features two separate reference clock inputs, REFA
and REFB. These inputs can be configured to accept differential
or single-ended signals. REFA and REFB are self biased in
differential mode and high impedance in single ended CMOS
mode. If REFA or REFB is driven single-ended, decouple the
unused side (REFA, REFB) via a suitable capacitor to a quiet
ground. These inputs may be dc-coupled, but set the dc
operation point as specified in the Specifications section.
The differential reference input receiver is powered down when
the differential reference input is not selected, or when the PLL1
is powered down. The single-ended buffers power down when
the PLL1 is powered down, when their respective individual
power-down registers are set, or when the differential receiver is
selected.
PLL1 Loop Filter
The PLL1 loop filter is mostly external from LF1 (Pin 7) to
ground. The value of the external components depend on the
external VCXO and the configuration parameters, such as input
clock rate and desired PLL1 loop bandwidth.
Figure 28. PLL1 Loop Filter
An external RC low-pass filter is recommended at the VCXO_VT
output for the best noise performance at 1 kHz offset. The pole
of this filter must be sufficiently high enough in frequency to
avoid stability problems with the PLL loop bandwidth.
Figure 29. Input PLL (PLL1) Block Diagram
CEXT_POLE
REXT_ZERO
LF1EXT_CAP
RPOLE2
165kΩ
CPOLE2
72pF
CHARGE
PUMP
TO
EXTERNAL
VCXO
LF1
BUFFER
1kΩ
0.47µF
VCXO_VT
OPTIONAL
FILTER
AD9528
SWITCH-
OVER
CONTROL
CHARGE
PUMP
LOCK
DETECT
REFA
LF1
VCXO_VT
VCXO_IN
VCXO_IN
REFA
REF_SEL
RA
RB
P
F
D
VCXO
REFB
REFB
AD9528
N1
10-BIT
DIVIDER
10-BIT
DIVIDER
PLL 1
10-BIT
DIVIDER
LOOP
FILTER



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