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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MB91F467DA датащи(PDF) 37 Page - Cypress Semiconductor |
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MB91F467DA датащи(HTML) 37 Page - Cypress Semiconductor |
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37 / 137 page  Document Number: 002-04613 Rev. *A Page 37 of 137 MB91460D Series 9.4.2 Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory’s Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MBM29LV400TC External pins FR-CPU mode MB91F465DA, MB91F467Dx external pins Comment Flash memory mode Normal function Pin number — INITX — INITX 73 RESET — FRSTX P09_6 60 — — MD_2 MD_2 70 Set to ‘1’ — — MD_1 MD_1 71 Set to ‘1’ — — MD_0 MD_0 72 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX P09_0 56 BYTE Internally fixed to ’H’ BYTEX P09_2 58 WE Internal control signal + control via interface circuit WEX P13_2 191 OE OEX P13_1 190 CE CEX P13_0 189 — ATDIN P25_7 187 Set to ‘0’ — EQIN P25_6 186 Set to ‘0’ — TESTX P09_3 59 Set to ‘1’ — RDYI P09_1 57 Set to ‘0’ A-1 Internal address bus FA0 P25_5 185 Set to ‘0’ A0 to A3 FA1 to FA4 P27_0 to P27_3 158 to 161 A4 to A7 FA5 to FA8 P27_4 to P27_7 164 to 167 A8 to A11 FA9 to FA12 P26_0 to P26_3 168 to 171 A12 to A15 FA13 to FA16 P26_4 to P26_7 174 to 177 A16 to A19 FA17 to FA20 P25_0 to P25_3 178 to 181 — FA21 P25_4 184 Not needed on MB91F465DA; Set to ‘1’ on MB91F467Dx DQ0 to DQ7 Internal data bus DQ0 to DQ7 P03_0 to P03_7 192 to 199 DQ8 to DQ15 DQ8 to DQ15 P02_0 to P02_7 200 to 207 |
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