For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

18

HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Figure 13. Delayed Lock Detect Window

For most applications the analog one shot window is sufficient. to determine the required Lock Detect one shot

window size:

required LD one Shot Window = (cP Phase offset (ns) + 8xtvco) x 1.3.

Cycle Slip Prevention (CSP)

When changing frequencies the Vco is not yet locked to the reference and the phase difference at the PFD varies

rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π,

the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to

low gain, when the phase difference is slightly larger than a multiple of 0 radians. this phenomena is known as cycle

slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in

Figure 14. cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal

Laplace analysis.

the HMc702LP6cE PFD features cycle Slip Prevention (cSP), an ability to virtually eliminate cycle slipping during

acquisition. When enabled, the cSP feature essentially holds the PFD gain at maximum until such time as the frequency

difference is near zero. cSP allows significantly faster lock times as shown inFigure 14. the use of the cSP feature is

cSP will cause the Vco n divider to momentarily divide by a higher or lower n value in order to pull the divided Vco

phase back towards the reference edge. the maximum recommended Vco n divider deviation is no more than

20% of the target n value programmed into register F. For example, if n=50 for the target frequency, then the cSP

Magnitude should be 10 or less so register 1ch Bits [3:0] would be programmed to ah.

in situations where the target n value is low, for example 36 the cSP behavior will be compromised because the

minimum Vco divide value is 32.

Figure 14. Cycle Slip Prevention (CSP)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D