HMC702LP6CE datasheet(16/38 Pages) AD

16 / 38 page

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HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

With this simplification the single sideband integrated Vco phase noise, Ф2 , in rads2 at the phase detector is given by

(EQ 9)

where

Ф2 SSB(ƒ0) is the single sideband phase noise in rads2/Hz inside the loop bandwidth, B is the 3 dB corner frequency of

the closed loop PLL and n is the division ratio of the prescaler

the rms phase jitter of the Vco in rads, Ф , results from the power sum of the two sidebands:

Ф = √ 2Ф

SSB

(EQ 10)

Since the simple integral of (EQ 9) is just a product of constants, we can easily do the integral in the log domain.

For example if the Vco phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is

100 kHz, and the division ratio n=100, then the integrated single sideband phase noise at the phase detector in dB is

given by Ф2dB = 10log (Ф2(ƒ0)Bπ ⁄ n2) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently Ф = 10-82/20 = 56 urads rms or

3.2 milli-degrees rms.

While the phase noise reduces by a factor of 20logn after division to the reference, the jitter is a constant.

the rms jitter from the phase noise is then given by Tjnp = Tref Ф / 2π

in this example if the reference was 50 MHz, Tref = 20 nsec, and hence Tjpn = 178 femto-sec.

a normal 3 sigma peak-to-peak variation in the arrival time therefore would be

±3

√ 2Tjpn = 0.756 ps

if the synthesizer was in fractional mode, the fractional modulation of the Vco divider will dominate the jitter. the exact

standard deviation of the divided Vco signal will vary based upon the modulator chosen, however a typical modulator

will vary by about ±3 Vco periods, ±4 Vco periods, worst case.

if, for example, a nominal Vco at 5 GHz is divided by 100 to equal the reference at 50 MHz, then the worst case

division ratios will vary by 100±4. Hence the peak variation in the arrival times caused by Δ∑ modulation of the

fractional synthesizer at the reference will be

(EQ 11)

PFD Jitter and Lock Detect Background (Continued)

in this example, tjΔ∑pk = ±200 ps(108-92)/2 = ±1600 psec. if we note that the distribution of the delta sigma modulation

is approximately gaussian, we could approximate tjΔ∑pk as a 3 sigma jitter, and hence we could estimate the rms jitter

of the Δ∑ modulator as about 1/3 of tjΔ∑pk or about 532 psec in this example.

Hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the Vco would be given

by the rms sum , where

(EQ 12)

in this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at

the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation.

Bottom line, we have to expect about ±1.6 nsec of normal variation in the phase detector arrival times when in

fractional mode. in addition, lower Vco frequencies with high reference frequencies will have much larger variations.,

for example, a 1 GHz Vco operating at near the minimum nominal divider ratio of 72, would, according to (EQ 11),

exhibit about ±4 nsec of peak variation at the phase detector, under normal operation. the lock detect circuit must not

confuse this modulation as being out of lock.

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rights of third parties that may result from its use. Specifications subject to change without notice. No

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