For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

9

HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Reference Path ’R’ Divider

at up to 250 MHz by numbers from 1 to 16,383. the selected input reference source may be divided or bypassed

(rfp_div_select), and applied to the phase detector reference input.

Reference Path Test Features

a fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with

a nearly randomly modulated delta-sigma digital modulator.

clean spur free operation of the synthesizer requires proper board layout of power and grounds. Spurious sources

are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating

frequency of the Vco, or they may arise from repeating patterns in the digital modulation itself . the loop filter and the

fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation

of the spurious products comes from layout issues. the problem is how to identify the sources of spurious products

if they occur?

the reference path of the HMc702LP6cE features some interesting test options for clocking the digital portion of the

synthesizer which may provide for a better understanding of the source of reference spurs should they occur. See

For normal operation, reg3h[15]=1. When reg3h[15]=1, (rfp_auto_refdiv select enabled) then reg 3 [14] & reg 1 [2]

are ignored. if reg 3 [13:0] is programmed to >=2, refDiv will be enabled and the divided output will be fed to the PFD.

if reg 3 [13:0] is programmed to 1, refDiv will be disabled and the undivided reference signal will be fed to the PFD.

When reg3h[15]=0 (rfp_auto_refdiv select disabled), then the state of the refDiv is controlled by reg 3 [14] & reg

1 [2]. then to enable refDiv reg 1 [2] = 1. to pass the divided reference signal to the PFD, reg 3 [14]=1. if reg

3 [14]=0, the undivided reference is passed directly to the PFD. this configuration would typically only be used for

engineering test. it allows the refDiv to be running while the PFD is operating with the undivided reference. this

allows inspection for spurs that may be manifest from the divider running.

it is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally

fall directly on the Vco frequency. We might chose for example to use the sine source (rfp_buf_sine_sel=1, div_

todig_en=0) to drive the reference divider. in such a case the delta sigma modulator is not normally used, however if

(sqr_todig_en=1 and dsm_xref_sin_select=0). this would allow the square wave clock to be set independently of

the locked integer mode Vco, and hence measure the coupling of the digital to the sidebands of the Vco at various

frequencies. Such a test can help in identifying and debugging grounding and layout issues in the application circuit

related to the digital portion of the PcB should they occur. in general it is recommended to follow the suggested layout

closely to avoid any such problems.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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