HMC702LP6CE datasheet(12/38 Pages) AD

12 / 38 page

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HMC702LP6CE

v10.0812

14 GHz 16-BIT FRACTIONAL-N PLL

Lock Detect Windows (gpo_sel=2)

Setting register gpo_sel = 2 (Reg1Bh<3:0> table 32) results in the lock detect window (Figure 12) and the phase

frequency detector UP and Dn output control signals (Figure 15) to be routed to pins GPo1, GPo3 and GPo2

respectively. this option gives insight into the Lock Detection Process and could allow the synthesizer to be used with

an external charge pump.

Figure 7. gpo_02 Outputs

Anti-cycle Slip Waveforms (gpo_sel = 3)

Setting register gpo_sel=3 (Reg1Bh<3:0> table 32) gives visibility into the anti-cycle slipping function of the PFD

as described in section Cycle Slip Prevention (cSP). three waveforms, reference path freq > Vco path freq, vco

path freq > ref path freq, and a PFD strobe which holds the PFD at maximum gain, are routed to GPo3, GPo2, and

GPo1 respectively. these lines will be active during frequency pull-in and will indicate instantaneously which signal,

reference or vco path is greater in frequency. the PFD strobe gives insight into when the PFD is near maximum gain

at 2π. the PFD strobe will be active until the Vco pulls into lock.

Internal Synchronized Frac strobe with clocks (gpo_sel= 4)

Setting register gpo_sel=4 in (Reg1Bh<3:0> table 32) gives visibility into the internally synchronized strobe that

is generated when commanding a frequency change by writing to the frac register. the internal strobe initiates the

update to the fractional modulator. the internal frac strobe, the ref path divider output and the sine reference input are

buffered out to GPo1, GPo2 and GPo3 respectively as shown in Figure 8. in this mode, GPo1 may be used to trigger

an external instrument when doing frequency hopping tests for example.

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