HT46C22 datasheet(22/46 Pages) HOLTEK

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HT46R22/HT46C22

Rev. 1.10

October 2, 2002

SRW bit

The SRW bit means that the master device wants to

read from or write to the I

2C BUS. The slave device

check this bit to understand itself if it is a transmitter or a

receiver. The SRW bit is set to

²1² means that the mas-

ter wants to read data from the I

2C BUS, so the slave de-

vice must write data to a bus as a transmitter. The SRW

is cleared to

²0² means that the master wants to write

data to the I

2C BUS, so the slave

device must read data from the I

2C BUS as a receiver.

Acknowledge bit

One of the slave device generates an acknowledge signal,

when the slave address is matched. The master device

can check this acknowledge bit to know if the slave device

accepts the calling address. If no acknowledge bit, the

master must send a STOP bit and end the communication.

When the I

2C BUS status register bit 6 HAAS is high, it

means the address is matched, so the slave must check

SRW as a transmitter (set HTX) to

²1² or as a receiver

(clear HTX) to

²0².

Data byte

The data is 8 bits and is sent after the slave device has

acknowledges the slave address. The first bit is MSB

and the 8th bit is LSB. The receiver sends the acknowl-

edge signal (

²0²) and continues to receive the next 1

byte data. If the transmitter checks and there

¢snoac-

knowledge signal, then it release the SDA line, and the

master sends a STOP signal to release the I

2C BUS.

The data is stored in the HDR register. The transmitter

must write data to the HDR before transmit data and the

receiver must read data from the HDR after receiving

data.

Receive acknowledge bit

When the receiver wants to continue to receive the next

data byte, it generates an acknowledge bit (TXAK) at

the 9th clock. The transmitter checks the acknowledge

bit (RXAK) to continue to write data to the I

2C BUS or

change to receive mode and dummy read the HDR reg-

ister to release the SDA line and the master sends the

STOP signal.

S C L

S D A

Stop bit

S C L

S D A

Start bit

S C L

S D A

S t a r t b i t

D a t a

s t a b l e

D a t a

a l l o w

c h a n g e

S t o p b i t

Data stable and data allow change

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