HT46C22 datasheet(9/46 Pages) HOLTEK

9 / 46 page

HT46R22/HT46C22

Rev. 1.10

October 2, 2002

Indirect addressing register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation of

[00H] accesses data memory pointed to by MP (01H).

Reading location 00H itself indirectly will return the re-

sult 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register.

The bit 7 of MP is undefined and reading will return the

result

²1². Any writing operation to MP will only transfer

the lower 7-bit data to MP.

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

Arithmetic and logic unit

- ALU

This circuit performs 8-bit arithmetic and logic operations.

The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but

also changes the status register.

Status register

- STATUS

This 8-bit register (0AH) contains the 0 flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PD), and watchdog time-out flag (TO).

It also records the status information and controls the

operation sequence.

With the exception of the TO and PD flags, bits in the

status register can be altered by instructions like

most other registers. Any data written into the status

operations related to the status register may give dif-

ferent results from those intended. The TO flag can

be affected only by system power-up, a WDT

time-out or executing the

²CLR WDT² or ²HALT² in-

struction. The PD flag can be affected only by exe-

cuting the

²HALT² or ²CLR WDT² instruction or a

system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

Interrupt

The device provides an external interrupt, an internal

timer/event counter interrupt, the A/D converter interrupt

and the I

2C BUS interrupts. The interrupt control register

0 (INTC0;0BH) and interrupt control register 1

(INTC1;1EH) contains the interrupt control bits to set the

enable or disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit of INTC0 and INTC1

may be set to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if the

related interrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must be pre-

vented from becoming full.

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the

²CLR WDT² instruction. PD is set by execut-

ing the

²HALT² instruction.

TO is cleared by system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set

by a WDT time-out.

6, 7

Unused bit, read as

²0²

Status register

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