HT46C22 datasheet(14/46 Pages) HOLTEK

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HT46R22/HT46C22

Rev. 1.10

October 2, 2002

Timer/Event Counter

A timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an 8-bit

programmable count-up counter and the clock may come

from an external source or the system clock.

Using the internal system clock, there is only one refer-

ence time-base. The internal clock source comes from

fSYS. Using external clock input allows the user to count

external events, measure time internals or pulse widths,

or generate an accurate time base. While using the in-

ternal clock allows the user to generate an accurate time

base.

There are two registers related to the timer/event counter;

TMR ([0DH]), TMRC ([0EH]). Two physical registers are

mapped to TMR location; writing TMR makes the starting

value be placed in the timer/event counter preload register

and reading TMR gets the contents of the timer/event

counter. The TMRC is a timer/event counter control regis-

ter, which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock. The

pulse width measurement mode can be used to count the

high or low level duration of the external signal (TMR). The

counting is based on the fINT.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current con-

tents in the timer/event counter to FFH. Once overflow oc-

curs, the counter is reloaded from the timer/event counter

preload register and generates the interrupt request flag

(TF; bit 5 of INTC) at the same time.

In the pulse width measurement mode with the TON

and TE bits equal to 1, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

transient occurs again. In other words, only 1 cycle mea-

surement can be done. Until setting the TON, the cycle

measurement will function again as long as it receives

further transient pulse. Note that, in this operating mode,

the timer/event counter starts counting not according to

the logic level but according to the transient edges. In

the case of counter overflows, the counter is reloaded

from the timer/event counter preload register and issues

the interrupt request just like the other two modes. To

enable the counting operation, the timer ON bit (TON;

bit 4 of TMRC) should be set to 1. In the pulse width

measurement mode, the TON will be cleared automati-

cally after the measurement cycle is completed. But in

the other two modes the TON can only be reset by in-

structions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writinga0toETIcan disable the interrupt

service.

In the case of timer/event counter OFF condition, writ-

ing data to the timer/event counter preload register will

also reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow oc-

curs. When the timer/event counter (reading TMR) is read,

the clock will be blocked to avoid errors. As clock blocking

may results in a counting error, this must be taken into con-

sideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate the PFD signal.

Label

(TMRC)

Bits

Function

PSC0~

PSC2

0~2

To define the prescaler stages, PSC2,

PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

To define the TMR active edge of

timer/event counter

(0=active on low to high; 1=active on

high to low)

TON

To enable or disable timer counting

(0=disabled; 1=enabled)

Unused bit, read as

²0²

TM0

TM1

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC register

Input/output ports

There are 19 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC and PD, which

are mapped to the data memory of [12H], [14H], [16H]

and [18H] respectively. All of these I/O ports can be

used for input and output operations. For input opera-

tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

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