HT46C22 datasheet(8/46 Pages) HOLTEK

8 / 46 page

HT46R22/HT46C22

Rev. 1.10

October 2, 2002

Stack register - STACK

This is a special part of the memory which is used to

save the contents of the program counter (PC) only. The

stack is organized into 6 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a

²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 6 return ad-

dresses are stored).

Data memory - RAM

The data memory is designed with 92

´8 bits. The data

memory is divided into two functional groups: special

function registers and general purpose data memory

(64

´8). Most are read/write, but some are read only.

The special function registers include the indirect ad-

dressing register (00H), timer/event counter register

(TMR;0DH), timer/event counter control register

(TMRC;0EH), program counter lower-order byte regis-

ter (PCL;06H), memory pointer register (MP;01H), ac-

cumulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register 0 (INTC0;

0BH), PWM data register (PWM;1AH), the I

2C BUS

slave address register (HADR;20H), the I

2C BUS con-

trol register (HCR;21H), the I

2C BUS status register

(HSR;22H), the I

2C BUS data register (HDR;23H), the

A/D result lower-order byte register (ADRL;24H), the

A/D result higher-order byte register (ADRH;25H), the

A/D control register (ADCR;26H), the A/D clock setting

PC;16H, PD;18H) and I/O control registers (PAC;13H,

PBC;15H, PCC;17H, PDC;19H). The remaining space

before the 40H is reserved for future expanded usage

and reading these locations will get

²00H². The general

purpose data memory, addressed from 40H to 7FH, is

used for data and control information under instruction

commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer register (MP;01H).

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 . H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 . H

: U n u s e d

R e a d a s " 0 0 "

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 6 4 B y t e s )

7 . H

4 0 H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

3 . H

I n d i r e c t A d d r e s s i n g R e g i s t e r

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C 0

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M

I N T C 1

H A D R

H C R

H S R

H D R

A D R L

A D R H

A D C R

A C S R

RAM mapping

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